Intel Corporation

Nick Lindert

Justin K Brask

Walid M Hafez

Chia-Hong Jan

Swaminathan Sivakumar

Anand S Murthy

Brian S Doyle

Mark T Bohr

Mark Y Liu

Robert S Chau

Szuya S Liao

Steven J Keating

Sridhar Govindaraju

Sairam Subramanian

Andrew N Westmeyer

Christopher Kenyon

Jack T Kavalieros

Matthew V Metz

Suman Datta

Stephen M Cea

Dinesh Somasekhar

Leonard P Guler

Joseph M Steigerwald

Timothy E Glassman

Satyarth Suri

Nadia M Rahhal-Orabi

Mitchell C Taylor

Ian R Post

Giuseppe Curello

Lana Jong

Lin Sha

Tahir Ghani

Mark L Doczy

Biswajeet Guha

Boyan Boyanov

Christopher J Jezewski

Scott A Hareland

Kevin X Zhang

Jack Hwang

Gilbert W Dewey

Ravi Pillarisetty

Glenn A Glass

Uday Shah

Yih Wang

Reza Arghavani

Markus Kuhn

Kanwal Jit Singh

Roman W Olac-Vaw

Ying Zhou

Sunit Tyagi

M Clair Webb

Christopher G Parker

Stephen Wu

Andre Baran

James R Mueller

Kirk Althoff

Keith M Jackson

Pauline N Jacob

Christine M Finnie

Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material

Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

Dual self-aligned gate endcap (SAGE) architectures

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls

A method for fabricating a semiconductor structure includes forming a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is formed over a first of the plurality of semiconductor fins. A second gate structure is formed over a second of the plurality of semiconductor fins. A gate edge isolation structure is formed laterally between and in contact with the first gate structure and the second gate structure, the gate edge isolation structure on the trench isolation region and extending above an uppermost surface of the first gate structure and the second gate structure. A precision resistor is formed on the gate edge isolation structure, wherein the precision resistor and the first gate structure and second gate structure comprise a same material layer.

Cost effective precision resistor using blocked DEPOP method in self-aligned gate endcap (SAGE) architecture

Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material

Methods and architectures for self-aligned build-up of patterned features. An initial patterned feature aspect ratio may be maintained or increased, for example to mitigate erosion of the feature during one or more subtractive device fabrication processes. A patterned feature height may be increased without altering an effective spacing between adjacent features that may be further relied upon, for example to further pattern an underlying material. A patterned feature may be conformally capped with a material, such as a metal or dielectric, in a self-aligned manner, for example to form a functional device layer on an initial pattern having a suitable space width-to-line height aspect ratio without the use of a masked etch to define the cap.

Self-aligned build-up of topographic features

Techniques are disclosed for improving gate control over the channel of a transistor, by increasing the effective electrical gate length (L) through deposition of a gate control layer (GCL) at the interfaces of the channel with the source and drain regions. The GCL is a nominally undoped layer (or substantially lower doped layer, relative to the heavily doped S/D fill material) that can be deposited when forming a transistor using replacement S/D deposition. The GCL can be selectively deposited in the S/D cavities after such cavities have been formed and before the heavily doped S/D fill material is deposited. In this manner, the GCL decreases the source and drain underlap (X) with the gate stack and further separates the heavily doped source and drain regions. This, in turn, increases the effective electrical gate length (L) and improves the control that the gate has over the channel.

Transistor device with gate control layer undercutting the gate dielectric

Embodiments of the present disclosure describe techniques for filling a high aspect ratio, narrow structure with multiple metal layers and associated configurations. In one embodiment, an apparatus includes a transistor structure comprising a semiconductor material, a dielectric material having a recess defined over the transistor structure, the recess having a height in a first direction, an electrode terminal disposed in the recess and coupled with the transistor structure, wherein a first portion of the electrode terminal comprises a first metal in direct contact with the transistor structure and a second portion of the electrode terminal comprises a second metal disposed on the first portion and wherein an interface between the first portion and the second portion is planar and extends across the recess in a second direction that is substantially perpendicular to the first direction. Other embodiments may be described and/or claimed.

Technique for filling high aspect ratio, narrow structures with multiple metal layers and associated configurations

Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.

Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layers

Semiconductor structures having capacitors and metal wiring integrated in a same dielectric layer are described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. Metal wiring is disposed in each of the dielectric layers. The metal wiring is electrically coupled to one or more of the semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers. The MIM capacitor is electrically coupled to one or more of the semiconductor devices.

Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer

Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

Formation of DRAM capacitor among metal interconnect

A method of patterning a metal () on a vertical sidewall () of an excavated feature () includes placing a material () in the excavated feature such that a portion () of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor () suitable for an eDRAM device.

Embedded memory device having MIM capacitor formed in excavated structure

A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective.

Rectangular capacitors for dynamic random access (DRAM) and dual-pass lithography methods to form the same

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Beaverton, OR, United States of America

Nick Lindert