Advanced Micro Devices Corporation

Nick Kepler

Larry Lingjer Wang

Christopher F Lyons

Olov B Karlsson

Effiong Etukudo Ibok

Basab Bandyopadhyay

Paul Raymond Besser

Karsten Wieczorek

Jeremy Isaac Martin

Christian Zistl

Fred Cheung

Eric M Apelgren

Jonathan B Smith

Basab Bandyophadhyay

Srikantewara Dakshina-Murthy

Basab Bandyopadhyah

Effiong Obok

An insulated trench isolation structure is formed by ion implanting impurities proximate to the trench edges for enhancing the oxidation rate and, hence, increasing the thickness of the oxide at the trench edges. Embodiments include ion implanting impurities prior to growing an oxide liner. The resulting thick oxide on the trench edges avoids overlap of a subsequently deposited polysilicon layer and breakdown problems attendant upon a thinned gate oxide at the trench edges.

Shallow trench isolation formation with ion implantation

A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.

Sidewall treatment for low dielectric constant (low K) materials by ion implantation

High integrity cobalt silicide contacts are formed with shallow source/drain junctions. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, followed by silicidation and diffusing impurities from a doped film during or after silicidation in an environment which discourages out-diffusion of the impurities to the environment. The resulting source/drain junctions are self-aligned to the cobalt silicide/silicon substrate interface, thereby preventing junction leakage while advantageously enabling forming the cobalt silicide contacts at optimum thickness to avoid parasitic series resistances. The formation of self-aligned source/drain junctions to the cobalt silicide/silicon substrate interface facilitates reliable device scaling, while the avoidance of unwanted diffusion of impurities to the environment assures adequate doping of the source/drain regions.

Prevention of dopant out-diffusion during silicidation and junction formation

An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.

Shallow trench isolation formation with two source/drain masks and simplified planarization mask

A method for forming ultra shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process due to grain boundary induced stress induced junction spiking amorphizes the metal layer prior to annealing during silicidation. After the gate and source/drain junctions are formed in a semiconductor device, dopant or non-dopant material is implanted into the anamorphous metal layer that has been previously deposited over the gate and source/drain junctions. The ion implantation is performed at an energy level sufficient to amorphize the metal (e.g. cobalt), and substantially eliminate grain boundaries in the metal and release grain boundary induced stress. This prevents grain boundary stress induced diffusion of the metal during the first phase of the silicidation process, where the metal is the diffusing species. The silicide regions that are formed during subsequent annealing steps therefore do not exhibit junction spikes.

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer

A method for forming ultra shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process amorphizes the semiconductor material in the gate and source/drain junctions prior to the deposition of the metal during silicidation. After the gate and source/drain junctions are formed in a semiconductor device, non-dopant material, such as silicon or germanium, is implanted into the semiconductor material in an unmasked implantation procedure. This highly controllable implanting creates amorphous silicon regions with a substantially smooth interface with the crystalline silicon. When the silicide regions are formed during subsequent annealing steps, the silicide forms in a manner that follows the amorphous regions so that the silicide/silicon interface is also substantially smooth and junction leakage induced by silicidation is prevented.

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions

High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. A layer of cobalt and a cap layer of titanium or titanium nitride are deposited on a substrate above intended source/drain regions, followed by silicidation. Embodiments include low-temperature rapid thermal annealing to form a high-resistivity phase cobalt silicide, removing the cap layer, depositing a doped film on the first phase cobalt silicide, and heating, as by high-temperature rapid thermal annealing, to form a low-resistance cobalt silicide during which impurities from the doped film diffuse through the cobalt silicide into the substrate to form source/drain regions having junctions extending into the substrate a constant depth below the cobalt silicide/silicon substrate interface. In another embodiment, impurities are diffused from the doped film to form source/drain regions and self-aligned junctions following formation of the low-resistance phase cobalt silicide. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon substrate interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness to avoid parasitic series resistances, thereby facilitating reliable device scaling.

Formation of junctions by diffusion from a doped film at silicidation

Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.

Stepper alignment mark structure for maintaining alignment integrity

A method of forming metal silicide in a semiconductor wafer with reduced junction leakage introduces an alloy at cobalt grain boundaries within a cobalt layer that overlays a silicon layer. The alloy element can be precipitated during deposition of the cobalt and the alloy element, or by an intermediate anneal after deposition. The cobalt layer and the silicon layer are then annealed to form metal silicide regions. By precipitating an alloy at the cobalt grain boundaries, cobalt diffusion at the grain boundaries is retarded during a first rapid thermal annealing step. Bulk diffusion is encouraged, and a more uniform silicide film with reduced interface roughness is produced. Since the interface roughness is reduced with the methods of the present invention, junction leakage is reduced. This allows shallower junctions to be fabricated, leading to devices with improved performance.

Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal

An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate without a planarization mask or etch. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, followed by polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches. A second layer of insulating material is then deposited to fill seams in the insulating material above the small trenches and to fill steps in the insulating material above the large trenches. The insulating material is then planarized. Since the insulating material is partially planarized by the first polish and the seams and steps are filled by the second deposition, the resulting topography of the upper surface of the second layer of insulating material is small enough to enable a direct final polish without the need to create and implement a planarization mask and to perform an etch and mask removal, thereby reducing manufacturing costs and increasing production throughput.

Shallow trench isolation formation without planarization mask

High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. These are formed by depositing a layer of cobalt on a substrate above intended source/drain regions, and depositing a doped amorphous silicon film on the cobalt. Silicidation, as by rapid thermal annealing, is performed to form a low-resistance cobalt suicide while consuming the amorphous silicon film and diffusing impurities from the doped amorphous silicon film through the cobalt silicide into the substrate. The diffusion of the impurities forms shallow junctions extending into the substrate a substantially constant depth below the cobalt silicide/silicon substrate interface. The consumption of the amorphous silicon film during silicidation, which results in less consumption of substrate silicon, and formation of source/drain junctions self-aligned to the cobalt silicide/silicon substrate interface, enables the formation of ultra-shallow source/drain junctions without junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.

Formation of junctions by diffusion from a doped amorphous silicon film during silicidation

A method for forming ultra shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high resistivity metal silicide regions are formed on the gate and source/drain junctions. Silicon is then deposited in a layer on the high resistivity metal silicide regions. An annealing step is then performed to form low resistivity metal silicide regions on the gate and source/drain junctions. The deposited silicon is a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide (such as CoSi) to a low resistivity metal silicide (such as CoSi.sub.2). Since the additional silicon provided in the deposited layer is consumed, there is reduced consumption of the silicon from the ultra-shallow junctions, thereby preventing the bottom of the silicide regions from reaching the bottom of the source/drain junctions.

Method of forming ultra-shallow junctions in a semiconductor wafer with

A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region. Any narrow regions are then merged together with the preliminary expanded region to produce data representing a final expanded region, which is used to produce a mask employed to produce an even width trench about the perimeter of the composite layer. The computer then generates the mask according to the results achieved and the isolation trenches are etched. The resulting isolation trenches prevent short-circuits from occurring between the various electrical devices on the semiconductor device.

Method for generating limited isolation trench width structures and a

High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Emdodiments include forming field oxide regions, gates, spacers, and lightly doped implants, and then depositing a layer of oxide on a substrate. The oxide layer is masked to protect portions of the oxide layer located near the gate, where it is desired to have a shallow junction, then etched to expose portions of the intended source/drain regions where the silicided contacts are to be formed. A high-dosage source/drain implant is thereafter carried out to form deep source/drain junctions with the substrate where the oxide layer has been etched away, and to form shallower junctions near the gates, where the implant must travel through the oxide layer before reaching the substrate. A layer of cobalt is thereafter deposited and silicidation is performed to form metal silicide contacts over only the deep source/drain junctions, while the cobalt on the oxide layer (i.e., above the shallower junctions) does not react to form cobalt silicide, and is thereafter removed. The present invention provides ultra-shallow source-drain junctions near the gates for improved electrical characteristics, and deeper junctions away from the gates, with cobalt silicide contacts above only the deeper junction portions to avoid junction leakage, thereby facilitating reliable device scaling.

Multi-depth junction formation tailored to silicide formation

A semiconductor device and method of forming contacts for the semiconductor device performs a retrograde implant of dopant in the source/drain regions so that the concentration of the dopant within these regions is highest at a predetermined depth below the top surface of the substrate. This depth is made to coincide with the bottom surfaces of the silicide contacts at the source/drain regions. Since the bottom of the silicide contacts are located at the region of greatest doping concentration within the source/drain junctions, the contact resistance is maintained relatively low while the sheet resistance may be made lower by increasing the thickness of the silicide contacts.

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Saratoga, CA, United States of America

Nick Kepler