Lsi Logic Corporation

Lsi Corporation

Asml Netherlands B.v.

Avago Technologies General IP (singapore) Pte. Ltd.

Asml Holding N.v.

Suvolta, Inc.

Nicholas K Eib

Mario Garza

Keith K Chao

Neal Patrick Callan

Ebo H Croffie

John V Jensen

Nicholas F Pasch

Sheldon Aronowitz

Ranko L Scepanovic

Edwin R Jones

Richard D Schinella

Dusan Petranovic

Colin D Yates

Jon S Owyang

Helmut Puchner

Lav D Ivanovic

Ravindra Manohar Kapre

John Haywood

James P Kimball

Johannes Jacobus Matheus Baselmans

Ashok K Kapoor

Arno Jan Bleeker

Kars Zeger Troost

Louis John Markoya

Valeriy K Sukharev

Paul G Filseth

Shumay X Dou

Thomas G Mallon

Prabhakar Pati Tripathi

Christopher L Neville

Ratan K Choudhury

Jeffrey Dong

Xudong Xu

Gauri C Das

The present invention provides methods and apparatus for accomplishing optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.

Maskless vortex phase shift optical direct write lithography

The present invention provides methods and apparatus for accomplishing a optical direct write phase shift lithography. A lithography system and method are provided wherein a mirror array is configured to generate vortex phase shift optical patterns that are directed onto a photosensitive layer of a substrate. The lithography methods and systems facilitate pattern transfer using such vortex phase shift exposure patterns.

A method for annealing a semiconductor device having at least one polysilicon region formed on a substrate, comprises growing dielectric material on the substrate adjacent to the polysilicon region. The method continues by polishing a surface of the dielectric material and by depositing a layer of a semi-transparent material on both the surface of the dielectric material and the surface of the polysilicon region. The method concludes by annealing the semiconductor device.

Method for providing temperature uniformity of rapid thermal annealing

The present invention provides an optimized direct write lithography system using optical mirrors. That is, a maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used as a substitute for the traditional chrome on glass masks. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement. The direct-writing of a pattern portion may rely on a single mirror mode or a combination of modes.

Optimized mirror design for optical direct write

A method for obtaining an optimal reflectivity value for complex multilayer stacks is disclosed. Aspects of the present invention include generating a model of a multilayer stack and parameterizing each layer by a thickness and an index of refraction; allowing a user to input values for the parameters; calculating an extrema for a cost function of reflectivity R using the input parameter values; calculating sensitivity values S for the extrema points; and obtaining an optimal value by calculating a cost function R+S.

Reflectivity optimization for multilayer stacks

The tilt and position of individually controllable element are simultaneously adjusted to allow a greater range of contrasts to be achieved. This can also be used to compensate for cupping of individually controllable elements. Simultaneous adjustment of both the position and tilt of the individually controllable elements can be achieved by two electrodes operable over a range of values.

Lithographic apparatus and device manufacturing method, an integrated circuit, a flat panel display, and a method of compensating for cupping

The present invention provides methods and apparatus for accomplishing a phase shift lithography process using a off axis light to reduce the effect of zero order light to improve the process window for maskless phase shift lithography systems and methodologies. A lithography system is provided. The lithography system provided uses off axis light beams projected onto a mirror array configured to generate a phase shift optical image pattern. This pattern is projected onto a photoimageable layer formed on the target substrate to facilitate pattern transfer.

Process and apparatus for achieving single exposure pattern transfer using maskless optical direct write lithography

The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.

Process window compliant corrections of design layout

A method and system of optimizing the illumination of a mask in a photolithography process. A specific, preferred method includes the steps of: loading minimum design rules of a layout, loading exposure latitude constraints, loading mask error constraints, loading initial illumination conditions, simulating current illumination conditions, obtaining dose-to-print threshold from the minimum design rules (i.e., lines-and-space feature), applying OPC on the layout using the dose-to-print threshold, calculating DOF using the exposure latitude and mask error constraints, changing the illumination conditions in order to attempt to maximize common DOF with the exposure latitude and mask error constraints, and continuing the process until maximum common DOF is obtained.

OPC based illumination optimization with mask error constraints

The present invention provides methods and apparatus for accomplishing a strong phase shift direct write lithography process using reconfigurable optical mirrors. A maskless lithography system is provided. The maskless direct-write lithography system provided uses an array of mirrors configured to operate in a tilting mode, a piston-displacement mode, or both in combination. The controlled mirror array is used to generate strong phase shift optical patterns which are directed onto a photoimageable layer of a substrate in order to facilitate pattern transfer. In order to avoid constraining the system to forming edges of patterns aligned with the array of mirrors, gray-scale techniques are used for subpixel feature placement.

Process and apparatus for generating a strong phase shift optical pattern for use in an optical direct write lithography process

A process for measuring alignment of latent images in a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in a lower layer on the substrate comprises the steps of forming a test pattern in selected fields of a first layer on a semiconductor substrate, forming a layer of photoresist over the first layer, forming latent images in portions of the photoresist layer lying in the selected fields overlying the test pattern of the first layer; and measuring the alignment of the test pattern in the selected fields of the first layer with the overlying latent images in the photoresist layer using scatterometry. In a preferred embodiment, the test pattern formed in each of the selected fields in the first layer comprises a pattern of parallel spaced apart lines, and the latent images formed in the portions of the photoresist layer in the selected fields above the test pattern in the first layer also comprises a pattern of parallel spaced part lines, with the two sets of lines interspaced between one another and generally parallel to one another to form a diffraction pattern.

Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate

A process for etching oxide is disclosed wherein a reproducibly accurate and uniform amount of silicon oxide can be removed from a surface of an oxide previously formed over a semiconductor substrate by exposing the oxide to a nitrogen plasma in an etch chamber while applying an rf bias to a substrate support on which the substrate is supported in the etch chamber. The thickness of the oxide removed in a given period of time may be changed by changing the amount of rf bias applied to the substrate through the substrate support.

Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate

The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.

Method and apparatus for application of proximity correction with relative segmentation

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San Jose, CA, United States of America

Nicholas K Eib