Advanced Micro Devices Corporation

Spansion Llc.

Cypress Semiconductor Corporation

Nicholas H Tripsas

Mark T Ramsbey

Suzette Keefe Pangrle

Matthew S Buynoski

Arvind Halliyal

Uzodinma Okoroanyanwu

Minh Van Ngo

Zoran Krivokapic

Jeffrey Allan Shields

Wei Zheng

Steven C Avanzino

Michael K Templeton

Mark W Randolph

Michael A VanBuskirk

Sameer S Haddad

Kuo-Tung Chang

Kathleen R Early

Maria Chow Chan

Scott D Luning

Effiong Etukudo Ibok

Timothy J Thurgate

Daniel Sobek

Vei-Han Chan

Robert B Ogle

Jusuke Ogura

Jack F Thomas

Janet S Wang

Ramkumar Subramanian

Angela Tai Hui

Sergey D Lopatin

Mark S Chang

Richard Paul Kingsborough

An Chen

Manuj Rathor

Igor Sokolik

Fred T K Cheung

William G Leonard

Bhanwar Singh

Fei Wang

Christopher F Lyons

Tuan Duc Pham

Colin Stewart Bill

Unsoon Kim

Yider Wu

David Keating Foote

Richard C Blish

Hsingya Arthur Wang

Minh Quoc Tran

Hieu T Pham

Scott Luning

Tzu-Ning Fang

Ercan Adem

Patrick K Cheung

Jein-Chen Young

Ashok M Khathuria

Wei Daisy Cai

Jane V Oglesby

Nicolay F Yudanov

Jeffery A Shields

Bryan William Hancock

Suzette Paugrle

A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

Buried silicide local interconnect with sidewall spacers and method for making the same

In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

Test structures for development of metal-insulator-metal (MIM) devices

Disclosed are semiconductor memory devices containing a plastic substrate and at least one active device supported by the plastic substrate, the active device containing an organic semiconductor material. The semiconductor memory devices containing a plastic substrate may further contain a polymer dielectric and/or a conductive polymer.

Semiconductor device built on plastic substrate

Disclosed are organic semiconductor devices containing a copolymer layer that contains a polymer dielectric and a semiconducting polymer formed using actinic radiation. As initially formed, the copolymer layer has dielectric properties, but portions may selectively rendered conductive after those portions are exposed to actinic radiation. Also disclosed are methods of making the organic semiconductor devices. Such devices are characterized by light weight and robust reliability.

Processing a copolymer to form a polymer memory cell

The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers&#x2014;respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.

Stacked organic memory devices and methods of operating and fabricating

The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wordline and bitline). In one embodiment of the invention, a diode is implemented as the selection element within the same layer as one of the control lines. Production of the selection element within the same layer as one of the wordline and bitline reduces problems associated with vertical stacking, increases device yield and reduces related production costs. The invention also provides an efficient method of producing memory devices with the selection element in the same layer as one of the control lines.

Memory device with a selection element and a control line in a substantially similar layer

A method of manufacturing a semiconductor device includes forming an interface layer, a nitrided gate dielectric, a gate electrode, and source drain regions. The interface layer is formed in a substrate by laser processing. The nitrided gate dielectric is formed over the interface layer by laser processing. The gate electrode is formed over the substrate and the gate dielectric after the laser processing step, and source/drain regions are formed in the substrate proximate to the gate electrode.

Nitridation of gate oxide by laser processing

A system and method are disclosed for processing an organic memory cell. An exemplary system can employ an enclosed processing chamber, a passive layer formation component operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The passive layer is not exposed to air after formation of the passive layer and before formation of the organic semiconductor layer. As a result, conductive impurities caused by the exposure to air do not occur in the thin film layer, thus improving productivity, quality, and reliability of organic memory devices. The system can further employ a second electrode formation component operative to form a second electrode on the organic semiconductor layer.

System and method for processing an organic memory cell

One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a different multi-bit value. If the threshold voltage of the cell has drifted outside of the number of allowable voltage states, then the cell is recovered by adjusting at least one voltage boundary of at least one of the number of allowable voltage states.

Methods and systems for recovering data in a nonvolatile memory array

Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using preamorphization implants, and formation of a conductivity facilitating layer. According to another aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using a contact with a plasma, and formation of a conductivity facilitating layer.

Preamorphization to minimize void formation

Growing community of inventors

San Jose, CA, United States of America

Nicholas H Tripsas