Sandisk Technologies Inc.

Advanced Micro Devices Corporation

Western Digital Technologies, Inc.

Spansion Llc.

Cypress Semiconductor Corporation

Fasl LLC

Nian Niles Yang

Zhigang Wang

Tien-Chun Yang

Philip David Reusswig

Grishma Shah

Yonggang Wu

Sahil Sharma

Steven Theodore Sprouse

Aaron Lee

Chris Avila

Rohit Sehgal

Hyeon-Seag Kim

Guowei Wang

John JianShi Wang

Xin Sheng Guo

Jianmin Huang

Joanna Lai

Alexandra Bauche

Abhijeet Manohar

Sachit Chandra

Fan Wan Lai

Idan Alrod

Gautham Reddy

Zhenlei Shen

Yue-Song He

Xinde Hu

Uday Chandrasekhar

Jiang Li

Phil Reusswig

Dmitry Vaysman

Yichao Huang

Eran Sharon

Yehuda Hahn

Ting Luo

Deepak Raghu

Mark Shlick

Chris Nga Yee Avila

Evgeny Mekhanik

Boon-Aik Ang

Hsiao-Han Thio

Yan Li

Jian Feng Chen

Alexander Bazarsky

Hiroyuki Ogawa

Ariel Navon

Dana Lee

James Fitzpatrick

Yu Nan Sun

Jiahui Yuan

Kuo-Tung Chang

Amit P Marathe

Kulachet Tanpairoj

Zhizheng Liu

Yider Wu

Karin Inbar

Anubhav Khandelwal

Eran Erez

Nancy S Leong

Tiao-Hua Kuo

Idan Goldenberg

Kenneth Louie

Rami Rom

Preeti Yadav

Chao-Han Cheng

Chris Yip

Piyush Dhotre

Chris Nga Yee Yip

Prasanna Desai Sudhir Rao

Smita Aggarwal

Yiwei Song

Roi Kirshenbaum

Yingda Dong

Harish Reddy Singidi

Shenqing Fang

Takao Akaogi

Johnny C Chen

Darlene G Hamilton

Binh Quang Le

Mohan Dunga

Seungjune Jeon

Unsoon Kim

Daniel Edward Tuers

Liang Pang

Changyuan Chen

Biswajit Ray

William S Wu

Ekram Bhuiyan

Lee M Gavens

Pitamber Shukla

Michael A VanBuskirk

Xinmiao Zhang

Nan Lu

Xuehong Yu

Wei Daisy Cai

Hounien Chen

Lanlan Gu

Jim Fitzpatrick

Piyush Anil Dhotre

Zubin Patel

Zelei Guo

Aspects of a storage device, a host device, and a redundant array of independent disks (RAID) system including multiple storage devices and the host device are provided that provide power control and power loss handling. The host device and the storage devices in the RAID system may each include at least a memory, a controller coupled to the memory, and a power management circuit coupled to the memory and the controller. A storage device controller may receive rationed power from the host device or a RAID controller in the host device in response to a message from that storage device indicating a detected loss in supplied power. An amount of the rationed power is based on a program data rate of the storage device or a size of data from the host device or the RAID controller to be written to the memory. Thus, UGSDs may be detected and addressed.

SSD auxiliary battery power for handling ungraceful shutdown with host

Aspects of a storage device are provided that provide power control and power loss handling in a RAID system. The storage device may include a memory, a controller coupled to the memory, a power management circuit coupled to the memory and the controller, and a rechargeable battery coupled to the power management circuit. The controller may receive power supplied by a RAID controller, receive a notification of a loss in power supplied to another storage device, and cause the power management circuit to detect a charge of the rechargeable battery in response to the notification. The power management circuit may also detect another loss in power supplied by the RAID controller, cause the controller to send a message to the RAID controller indicating the loss in power, and receive power from the RAID controller in response to the message. As a result, UGSDs in RAID may be detected and addressed.

A method, apparatus, and system for level dependent error correction code protection in multi-level non-volatile memory. A write command to write data to a non-volatile memory array may be received. At least one multi-level page of multi-level storage cells may be determined for the write data. A coding rate for the write data of the at least one multi-level page may be determined based on an attribute of the at least one multi-level page. An ECC codeword may be generated that satisfies the coding rate and includes the write data. The ECC codeword may then be stored on the at least one multi-level page.

Level dependent error correction code protection in multi-level non-volatile memory

The present disclosure generally relates to efficient block usage after ungraceful shutdown (UGSD) events. After a UGSD event, a host device is alerted by the data storage device that a QLC block that was being used prior to the UGSD event is experiencing an ongoing block recovery and that the block is not yet available to accept new data. The block is then checked to determine whether the block can continue to be used for the programming that was occurring at the time of the UGSD event. Once a determination is made, the data storage device notifies the host device so that normal operations may continue. Additionally, the amount of free blocks available for programming is monitored during UGSD events so that the host device can be warned if a power loss halt is triggered.

Efficient data storage usage associated with ungraceful shutdown

For solid state drive (SSD) or other memory system formed of multiple memory dies, techniques are presented for operation in a standby mode with increased power savings. The memory dies are operable in a regular standby mode and in a low power standby mode. Based upon the amount of current each of the memory dies in the regular standby mode, when the device goes into standby the memory dies that draw higher amounts of current when in the regular standby mode are instead placed into the low power standby mode. The amount of current drawn by each of the memory die in the regular standby mode can be determined for each of the memory dies at die sort or as part of the memory test process, or can be determine by an assembled SSD itself.

Intelligent power saving mode for solid state drive (ssd) systems

A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.

Temperature variation compensation

A method and apparatus for dynamically determining when, or how often, to do a read scan operation on a solid-state storage drive. One solution adjusts a read scan interval as part of performing a read scan operation. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Then, a cross temperature metric for the storage block is determined. A read scan interval is changed in response to the cross temperature metric satisfying a cross temperature threshold. Then, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold.

Variable read scan for solid-state storage device quality of service

Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.

Using over provisioning space for selectively storing block parity

A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

Storage system and method for boundary wordline data retention handling

The present disclosure discloses a memory device including a control system for thermal throttling. The control system acquires the temperature of a non-volatile memory element from a temperature detector at a first frequency. Upon determining that the temperature of the non-volatile memory element is above a pre-determined threshold, the control system acquires the temperature of the non-volatile memory element from the temperature detector at a second frequency that is higher than the first frequency and activates the thermal throttling for the non-volatile memory element.

Thermal throttling for memory devices

A circuit configured to dynamically adjust data transfer speeds for a non-volatile memory die interface. The circuit includes an initialization circuit, a control circuit, a switch circuit, and a read-write circuit. The initialization circuit is configured to load multi-level cell settings that configure a memory interface for transfer of data for storage cells configured to store more than one bit per storage cell. The control circuit is configured to receive a read command that references single-level storage cells of a memory die. The switch circuit is configured to switch settings for the memory interface from the multi-level cell settings to single level cell settings, in response to receiving the read command. The read-write circuit is configured to read data for the read command from the memory die using the single level cell settings.

Dynamically adjust data transfer speed for non-volatile memory die interfaces

Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

Enhancing the effectiveness of read scan performance and reliability for non-volatile memory

Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.

Physical secure erase of solid state drives

Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.

Pre-program read to counter wordline failures

An exemplary method to rank blocks of a non-volatile memory device includes: for each of a plurality of blocks of a memory device, determining a respective erase health metric (EHM) for each of the blocks by combining an erase difficulty metric and an age metric, including: calculating the erase difficulty metric for a respective block based on erase performance metrics obtained during erase phases of an erase operation performed on the respective block, and determining the age metric for the respective block based on a total number of erase operations performed on the respective block during its lifespan. After determining the respective EHM for each of the blocks, the method includes ranking blocks in accordance with the determined respective EHMs, and selecting a block of the plurality of blocks in accordance with the rankings, and writing data to the selected block.

Erase health metric to rank memory portions

Growing community of inventors

Mountain View, CA, United States of America

Nian Niles Yang