International Business Machines Corporation

Nestor A Bojarczuk, Jr

Supratik Guha

Eduard Albert Cartier

Matthew Warren Copel

Vijay Narayanan

Vamsi Krishna Paruchuri

Rajarao Jammy

Cyril Cabral, Jr

Martin Michael Frank

Evgeni Petrovich Gousev

Richard Alan Haight

Arunava Gupta

Peter Richard Duncombe

Lars-Ake Ragnarsson

Joseph M Karasinski

Xinwei Li

Michael Patrick Chudzik

Richard Joseph Gambino

Paul Charles Jamison

Ralph R Ruf

Evgeni P c/o Ibm United Kingdom Limited Gousev

Martin M c/o Ibm United Kingdom Limited Frank

Rajarao c/o Ibm United Kingdom Limited Jammy

The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlON. The high k dielectric can be HfO, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/HOperoxide solution.

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics

A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.

Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming same

The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first stack of a pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET device is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics

The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.

Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS

A semiconductor structure is provided that includes a Vstabilization layer between a gate dielectric and a gate electrode. The Vstabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vstabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide

A data storage element (and method of forming the same) includes a substrate comprising a semiconductor material, a metal oxide layer including an electrically insulating rare earth metal oxide disposed upon a surface of the substrate, a conductive material disposed upon the metal oxide layer, a first electrode electrically connected to the conductive material, and a second electrode connected to the substrate.

Rare earth metal oxide memory element based on charge storage and method for manufacturing same

A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800&#xb0; C. and about 1000&#xb0; C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.

Dielectric stack without interfacial layer

A method of forming a layer of oxide or oxynitride upon a substrate including first placing a substrate having an upper surface and a lower surface in a high vacuum chamber and then exposing the upper surface to a beam of atoms or molecules, or both, of oxygen or nitrogen or a combination of same at a temperature sufficient to form a reacted layer on the upper surface of said substrate wherein said layer has a chemical composition different from the chemical composition of said substrate. The reacted upper layer is then exposed simultaneously in the chamber to atomic or molecular beams of oxygen, nitrogen or both and to a beam of metal atoms or metal molecules selected from the group consisting of Al, Si, Zr, La, Y, Sc, Sr, Ba, Ti, Ta, W, Cr, Zr, Ca, Mg, Be, Pr, Nd and Hf to form a metal oxide, a metal nitride or a metal oxynitride layer in said layer. Another option is to expose the upper surface of the substrate simultaneously in the chamber to atomic or molecular beams of oxygen, nitrogen or both and to a beam of metal atoms or meal molecules selected from the group consisting of Al, Si, Zr, La Y, Sc, Sr, Ba, Ti, Ta, W, Cr, Zr, Ca, Mg, Be, Pr, Nd and Hf to form a metal oxide, a metal nitride or a metal oxynitride layer on said reacted layer.

Engineered high dielectric constant oxide and oxynitride heterostructure gate dielectrics by an atomic beam deposition technique

A method of forming a dielectric stack device having a plurality of layers comprises the steps of providing a silicon substrate, forming a metal-oxide layer on a silicon oxide layer which is formed on the silicon substrate, and performing an annealing with respect to the metal-oxide layer and the silicon oxide layer until a silicate layer is formed to replace the metal-oxide layer and the silicon oxide layer is removed, wherein the annealing is performed at a temperature between about 800&deg; C. and about 1000&deg; C. for a time period between about 1 second and about 10 minutes. After forming the silicon oxide layer on the silicon substrate, the metal-oxide layer may be deposited on the silicon oxide layer. Alternatively, the metal-oxide layer may be deposited on the silicon substrate, and the silicon oxide layer grows between the metal-oxide layer and the silicon substrate. The metal-based oxide is preferably an Yttrium-based oxide.

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Poughkeepsie, NY, United States of America

Nestor A Bojarczuk, Jr