Industrial Technology Research Institute

Vanguard International Semiconductor Corporation

Neng-Wei Wu

Wen-Doe Su

A method for making semicrown stacked capacitors for DRAM devices is achieved. A first insulating layer, a second insulating etch-stop layer, and a high-etch-rate third insulating layer are sequentially formed on a substrate over the memory cell areas having FETs with source/drain areas. Recesses are etched in the third and second insulating layers for bottom electrodes, aligned over device areas. Node contact openings are plasma etched in the first insulating layer exposed in the recesses to one of each source/drain area. A first polysilicon layer is deposited to form node contacts and the bottom electrodes. A high-etch-rate fourth insulating layer is used to fill the recesses. The fourth insulating layer and the first polysilicon layer are etched or chem/mech polished back to form the array of bottom electrodes having oxide plugs. The plugs and third insulating layer are wet etched to the etch-stop layer to form the semicrown bottom electrodes. A thin dielectric layer is deposited, and a patterned second polysilicon layer is formed for top electrodes. The etch-stop layer, retained in the final structure, supports the bottom electrodes to reduce mechanical damage during subsequent processing and to also reduce the nonuniformity across the substrate for an improved photolithographic process window.

Method of forming semicrown-shaped stacked capacitors for dynamic random

A field effect transistor having a thin polycrystalline silicon layer as a channel region, a lower gate electrode beneath the silicon layer, and upper gate electrode with an offset above the silicon layer, and a gate dielectric layer between the lower gate electrode and the silicon layer, and a gate dielectric layer between the upper gate electrode and the silicon layer.

Offset dual gate thin film field effect transistor

A method of fabricating an offset dual gate thin film field offset transistor wherein a lower gate electrode is formed on an insulating substrate is provided. A dielectric layer deposited. A polycrystalline silicon layer deposited and patterned to overlie and extend beyond the edges of the lower gate. A dielectric layer deposited. A metal layer deposited. A photoresist layer deposited and patterned to define a upper gate electrode in the metal layer that overlies the lower gate electrode but extend beyond one edge. The exposed metal layer is removed to form the upper gate electrode. An impurity is ion implanted into the polycrystalline silicon layer to form source and drain regions, using the photoresist layer and metal layer as a mask.

Method of fabricating an offset dual gate thin film field effect

A method of forming a self-aligned metal oxide semiconductor (MOS) structure is described. Multilayer dielectrics are used at the edge of the gate electrode, and the gate electrode, the source and the drain have metal silicide regions. The first layer of dielectric is used to define a lightly doped drain (LDD) structure and the second dielectric layer serves to extend the oxide region at the gate edge and to improve the source/drain junction leakage property and to reduce the shorting percentage of gate to source/drain. A special device structure with extended lateral diffusion of junction under the oxide at the gate edge will be performed by using this method.

Double spacer salicide MOS device and method

A process for forming a thin film field effect transistor, particularly adapted for use in SDRAM devices using CMOS flip-flop circuits, wherein the transistor has a drain-channel P-N junction that is precisely spaced from the gate electrode, the process involving the etch back of the edge of the gate electrode, either prior to ion implantation to form the source and drain, or following the implantation.

Method of forming a thin film field effect transistor having a drain

A process for reducing gate sheet resistance in VSLI devices employs planarization and metal refilling to produce a gate of layers of polysilicon and pure metal. The polysilicon underlayer maintains the characteristics of a polysilicon gate and the metal layer reduces the gate sheet resistance. The process includes the etching back of the planarized dielectric (6) to expose the top surface of the polysilicon gate (3), the etching of the polysilicon to form a groove, and the filling of the groove with a metal, e.g. W, by selective or blanket CVD.

Growing community of inventors

Hsinchu, Taiwan

Neng-Wei Wu