Micron Technology Incorporated

Inotera Memories, Inc.

Other

Neng-Tai Shih

Shing-Yih Shih

Hsu Chiang

Tzung-Han Lee

Yaw-Wen Hu

Hsin-Chuan Tsai

Sheng-Hsiung Wu

Shih-Fan Kuan

Yi-Jen Lo

Yu Lung Chang

Kao-Mei Sung

Heng Hao Hsu

Hsiao-Lei Wang

An epitaxial substrate having a 2D material interposer, the epitaxial substrate extending along an epitaxial interface direction, wherein the epitaxial substrate includes: a polycrystalline base substrate having a superficial layer, a wafer bevel, and a back surface, wherein a difference in coefficient of thermal expansion between the polycrystalline base substrate and MN or GaN is not greater than 1.5×10° C.in a direction parallel to the epitaxial interface; a multi-orientation 2D ultra-thin material interposer arranged on the superficial layer of the polycrystalline base substrate, wherein the multi-orientation 2D ultra-thin material interposer has a top layer, a lattice constant of the top layer being highly matched with that of AlN, AlGaN, or GaN; and an AlN, AlGaN, or GaN-based epitaxial layer, which is epitaxially grown on a portion of the multi-orientation 2D ultra-thin material interposer distant from the polycrystalline base substrate.

Epitaxial substrate having a 2D material interposer, method for manufacturing the epitaxial substrate, and device prepared from the epitaxial substrate

A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

Apparatuses including dummy dice

A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Methods for forming semiconductor devices

Methods of forming microelectronic devices including dummy dice

A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

Microelectronic devices including redistribution layers

Microelectronic package structures including redistribution layers

Methods of forming and operating microelectronic devices including dummy chips

A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Semiconductor device

Semiconductor devices including dummy chips

Methods of fabricating a semiconductor package structure including at least one redistribution layer

A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the at least one conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the at least one conductive via.

Method for fabricating semiconductor package

A semiconductor device includes a semiconductor device includes an interposer having a first side and a second side opposite to the first side, wherein the interposer comprises a redistribution layer (RDL), and the RDL comprises a first passivation layer on the first side and a second passivation layer on the second side; at least one active chip mounted on the first passivation layer on the first side through a plurality of first bumps penetrating through the first passivation layer; a molding compound disposed on the first side, the molding compound covering the at least one active chip and a top surface of the first passivation layer; and a plurality of solder bumps mounted on the first passivation layer on the second side.

Wafer level package and fabrication method thereof

A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.

Semiconductor device and fabrication method therefor

A silicon interposer includes a silicon substrate having a front side and a rear side opposite to the front side; a first integrated circuit chip disposed in the front side of the silicon substrate; a second integrated circuit chip disposed in the front side of the silicon substrate and being in close proximity to the first integrated circuit chip; a dummy kerf region between the first integrated circuit chip and the second integrated circuit chip; and at least a circuit device disposed in the front side of the silicon substrate within the kerf region.

Silicon interposer and fabrication method thereof

A package-on-package (PoP) assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an interposer having a first side and a second side opposite to the first side, at least one chip mounted on the first side within a chip mounting area through a plurality of bumps, a molding compound disposed on the first side, the molding compound covering the at least one chip, and a plurality of peripheral bump structures penetrating through the molding compound within the peripheral area. Each of the peripheral bump structures includes conductive pillar and a partial TMV directly stacked on the conductive pillar. A plurality of solder balls is mounted on the second side of the interposer. The top die package is electrically connected to the peripheral bump structures.

Growing community of inventors

Taipei, Taiwan

Neng-Tai Shih