International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries Inc.

Lam Research Corporation

Adeia Semiconductor Solutions LLC

Tessera LLC

Nelson M Felix

Ekmini Anuja De Silva

Chi-Chun Liu

Indira P Seshadri

Sivananda K Kanakasabapathy

Sean David Burns

Jing Guo

Lawrence Alfred Clevenger

Christopher J Penny

Nicole A Saulnier

Yann A M Mignot

Yann Mignot

Dario Leonardo Goldfarb

Stuart A Sieg

Ashim Dutta

Roger Allan Quon

John Christopher Arnold

Matthew Earl Colburn

Abraham Arceo De La Pena

Christopher P Ausschnitt

Luciana Meli Thompson

Anuja E DeSilva

Rudy J Wojtecki

Daniel Sanders

Jennifer Church

Ruqiang Bao

Tao Li

Allen H Gabor

Daniel A Corliss

Praveen Joseph

Nicolas J Loubet

Joshua T Smith

Eric R Miller

Muthumanickam Sankarapandian

Robert L Bruce

Scott David Halle

Martin Glodde

Karen Elizabeth Petrillo

Bharat Kumar

Dominik Metzler

Kristin Schmidt

Cody John Murray

Alex Richard Hubbard

Luciana Meli

Bassem M Hamieh

Sean D Burns

Zhenxing Bi

Yongan Xu

Hoa D Truong

Derren Neylon Dunn

Ravi K Bonam

Jing Sha

Gangadhara Raja Muthinti

Siva Kanakasabapathy

Alan C Thomas

Eric Miller

Romain Lallement

Yasir Sulehria

Martha Inez Sanchez

Bhaskar Nagabhirava

Phillip Friddle

Matthew E Colburn

Roger A Quon

Chiew-Seng Koay

Scott S Halle

Ekimini Anuja De Silva

A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Alternating hardmasks for tight-pitch line formation

Embodiments of the invention include a dielectric reflow technique for boundary control in which a first layer is deposited on a first transistor region and a second transistor region, the first and second transistor regions being adjacent. A dielectric layer is formed to protect the second transistor region such that the first transistor region is exposed, the dielectric layer bounded at a first location. In response to removing a portion of the first layer on the first transistor region, the dielectric layer protecting the second transistor region is reflowed such that at least a reflowed portion of the dielectric layer extends beyond the first location.

Dielectric reflow for boundary control

Various embodiments herein relate to methods, apparatus, and systems that utilize a multi-layer hardmask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multi-layer hardmask includes (1) an upper layer that includes a metal-containing material such as a metal oxide, a metal nitride, or a metal oxynitride, and (2) a lower layer that includes an inorganic dielectric silicon-containing material. Together, these layers of the multi-layer hardmask provide excellent etch selectivity and reduce formation of defects such as microbridges and line breaks. Certain embodiments relate to deposition of the multi-layer hardmask. Other embodiments relate to etching of the multi-layer hardmask. Some embodiments involve both deposition and etching of the multi-layer hardmask.

Multi-layer hardmask for defect reduction in EUV patterning

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Self aligned pattern formation post spacer etchback in tight pitch configurations

A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Bottom source/drain etch with fin-cut-last-VTFET

A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.

Polymer brush adhesion promoter with UV cleavable linker

One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.

Spacer-defined process for lithography-etch double patterning for interconnects

An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

Inverse tone pillar printing method using organic planarizing layer pillars

Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.

EUV pattern transfer using graded hardmask

A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.

Fabrication of back-end-of-line interconnects

A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.

Self-aligned pattern formation for a semiconductor device

An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80&#xb0;.

Organic photoresist adhesion to metal oxide hardmasks

Growing community of inventors

Briarcliff Manor, NY, United States of America

Nelson M Felix