International Business Machines Corporation

Neena Garg

Kenneth John Giewont

Junedong Lee

Devendra K Sadana

Stephen Richard Fox

Anthony Gene Domenicucci

Dan Moy

Maurice Heathcote Norcott

Siegfried Lutz Maurer

Charles W Koburger, Iii

Arne Watson Ballantine

Dominic Joseph Schepis

Michael John Hargrove

Byeongju Park

Eric Adler

Gerd Pfeiffer

Richard J Murphy

Peter A Emmi

Donald L Wilson

Frank J Schmidt, Jr

Isabel Ying Yang

Walter J Frey

Terrance M Tornatore

Gregory D Pomarico

Michael E Adamcek

Thomas R Kupiec

Michael J Gambero

A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage V.

Control of buried oxide in SIMOX

A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.

Divot reduction in SIMOX layers

A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage V .

A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a &ldquo;touch-up&rdquo; O implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the &ldquo;touch-up&rdquo; O implant (second ion implant), which in turn would result in a leaky BOX.

Method of forming a body contact using BOX modification

A method of improving surface morphology of a semiconductor substrate when using an SOI technique comprises providing a silicon ingot positioned on a support member, orientating the silicon ingot in relation to the support member, and a cutting device, and cutting the silicon ingot along about a (100) crystal plane of the silicon ingot, preferably using a wire saw. This then provides a silicon substrate having an initial surface defining a miscut angle which is less than about 0.15 degrees from the (100) crystal plane. The method then comprises processing the silicon substrate using SIMOX processing, which includes implanting oxygen atoms in the silicon substrate to form a buried oxide layer and annealing the silicon substrate to provide a final substrate surface. Finally, the method includes accepting the final substrate surface for further processing when the final substrate surface measures between 2-20 &angst; RMS using an atomic force microscopy technique.

Surface roughness improvement of SIMOX substrates by controlling orientation of angle of starting material

A method to control the quality of a buried oxide region, and to substantially reduce or eliminate deep divots in SOI substrates is provided. Specifically, the inventive method includes the steps of implanting oxygen ions into a surface of a Si-containing substrate; and annealing the Si-containing substrate containing the implanted oxygen ion at a temperature of about 1300&deg; C. or above and in a chlorine-containing ambient so as to form a buried oxide region that electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. The chlorine-containing ambient employed in the annealing step includes oxygen and a chlorine-containing carrier gas such as HCl, methylene chloride, trichloroethylene and trans 1,2-dichloroethane.

Controlling internal thermal oxidation and eliminating deep divots in SIMOX by chlorine-based annealing

An apparatus and method for controlling wafer temperature and environment is provided. The apparatus includes a batch processing fixture for batch processing wafers at a first elevated temperature. The batch of wafers is not substantially ramped in temperature within the batch processing fixture. The apparatus also includes a single wafer processing apparatus for rapidly ramping temperature of a wafer of the batch from the first elevated temperature wherein a uniform temperature across the wafer is maintained during the ramping. Another embodiment of the apparatus ( ) includes an RTP chamber ( ) having an inert or reducing environment and that includes a pedestal ( ) for holding a single wafer ( ) and a heater unit ( ) arranged so as to uniformly and rapidly heat the single wafer. The apparatus also includes a cooling chamber ( ) having an inert or reducing environment and located adjacent the RTP chamber and selectively open thereto, and includes a pedestal ( ) for holding the single wafer, a first loading chamber ( ) having an inert or reducing environment and located adjacent the cooling chamber and selectively opened thereto, and having a cassette ( ) for holding one or more wafers. The apparatus also includes a thermal processing chamber ( ), such as an LPCVD furnace, located adjacent the loading chamber and arranged to receive the cassette so as to perform a thermal process of the wafers in the cassette.

Apparatus and method for controlling wafer environment between thermal clean and thermal processing

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Fishkill, NY, United States of America

Neena Garg