International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Mentor Graphics Corporation

Nazmul Habib

Jeanne P Bickford

Baozhen Li

Robert J McMahon

Pascal A Nsame

Tad Jeffrey Wilder

John Greg Massey

Emmanuel Yashchin

John Robert Goss

Ernest Y Wu

Carole D Graas

Deborah M Massey

Susan K Lichtensteiger

Bruce Balch

Jeanne P S Bickford

Troy Joseph Perry

Kerry Bernstein

Richard Stephen Graf

Janak G Patel

Theodoros Anemikos

Douglas S Dewey

Daniel D Reinhardt

Jeanne Paulette Spence Bickford

Manish Nayini

Mark A Burns

Chung H Lam

John J Ellis-Monaghan

Kanak Behari Agarwal

Eric A Foreman

Kerim Kalafala

Darren Lane Anand

Alvin Wayne Strong

Jerry D Hayes

Sebastian Theodore Ventrone

Rohit Pradeep Shetty

Igor Arsovski

Albert Manhee Chu

Norman Jay Rohrer

Wen Liu

Daniel Lawrence Stasiak

Thomas M Maffitt

Mark C H Lamorey

Richard Andre Wachnik

Daryl Michael Seitzer

Phung T Nguyen

Raymond J Rosner

Adam Charles Smith

Janice M Adams

Thomas S Barnett

Umberto Garofano

Jeanne P Spence Bickford

A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks.

Heat sink configuration for multi-chip module

An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

IC chip package with dummy solder structure under corner, and related method

An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur.

A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Optimization of integrated circuit reliability

A method and associated system. The method includes steps of: (a) a voltage bin is selected from of a set of voltage bins, each voltage bin having a different range of frequencies based on the highest operating frequency and the lowest operating frequency specified for an integrated circuit chip not previously tested; (b) a functional path test is performed on a selected path of a set of testable data paths of the integrated circuit chip not previously tested; (c) if the integrated circuit chip fails the functional path test, then a current supply voltage value is changed to a voltage value associated with a not previously selected voltage bin; (d) a not previously tested path of the set of testable paths is selected. Steps (b), (c) and (d) are repeated until every path of the set of testable paths has been tested.

Product performance test binning

Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

IC wafer for identification of circuit dies after dicing

Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

Integrated circuit chip reliability qualification using a sample-specific expected fail rate

A computer-implemented method for evaluating a circuit design to protect a plurality of metal connections from current pulse damage, the method includes receiving a circuit design including the plurality of metal connections and evaluating a maximum peak current of one or more of the plurality of metal connections. The method further includes determining a peak current threshold for the plurality of metal connections based on physical characteristics of the plurality of metal connection and responsive to determining that the maximum peak current of the one or more of the plurality of metal connections exceeds the peak current threshold, performing a peak current design modification to modify the plurality of metal connections in the circuit design.

Methodology to prevent metal lines from current pulse damage

A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.

Application of stress conditions for homogenization of stress samples in semiconductor product acceleration studies

The present disclosure generally provides for a method of managing semiconductor manufacturing defects. The method includes: determining a cumulative aging parameter for each of a plurality of first IC products produced with a particular manufacturing line, the cumulative aging parameter being dependent on a product operating condition; calculating an observed defect rate for the plurality of first IC products based on a difference between a predicted value of the aging parameter and the cumulative aging parameter for each of the plurality of first IC products; and adjusting a manufacturing reliability model for the particular manufacturing line in response to the observed defect rate being different from a predicted defect rate for the plurality of first IC products.

System and method for managing semiconductor manufacturing defects

A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of a set of voltages bins corresponding to frequency specification limits of an integrated circuit chip using functional testing of data paths of the integrated circuit chip.

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South Burlington, VT, United States of America

Nazmul Habib