Texas Instruments Corporation

Naweed Anjum

Michael G Amaro

Yiqi Tang

Liang Wan

Charles Allen DeVries

Makarand Ramkrishna Kulkarni

Dat Tan Nguyen

Thao To

David Maxwell

A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

Multi-layer semiconductor package with stacked passive components

In a described example, a method includes: providing a product package for a product die; building a product mimic die that mimics the product die and which is configured to make the product package functional for use in reliability testing; packaging the product mimic die in the product package to form a packaged product mimic die; reliability testing the packaged product mimic die; responsive to the reliability testing, revising the product package; and repeating the steps of reliability testing and revising the product package until the product package passes the reliability tests.

Electronic device package with board level reliability

A packaged electronic device includes a multilayer lead frame with first and second trace levels, a via level, an insulator, a conductive landing pad and a conductive crack arrest structure, the conductive landing pad has a straight profile that extends along a first direction along a side of the multilayer lead frame, the conductive crack arrest structure has a straight profile along the first direction and the conductive crack arrest structure is spaced from the conductive landing pad along an orthogonal second direction.

Electronic device with crack arrest structure

A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.

Recess lead for a surface mount package

An embodiment relates generally to a method of testing a mixed signal device. The method includes monitoring multiple parameters of the mixed signal device and scanning the mixed signal device with an optical source. The method also includes forming multiple windows, where each window is assigned to a respective parameter. The method further includes comparing an image from a respective image to a reference image to determine an existence of an anomaly.

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Murphy, TX, United States of America

Naweed Anjum