Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

University of Utah Research Foundation

Skhynix Inc.

Naveen Muralimanohar

Norman Paul Jouppi

Jichuan Chang

Parthasarathy Ranganathan

Doe Hyun Yoon

Rajeev Balasubramonian

Ali Shafiee Ardestani

Paolo Faraboschi

Erik Ordentlich

Robert S Schreiber

Alan Lynn Davis

Gregg Bernard Lesartre

Sheng Li

Aniruddha Nagendran Udipi

Brent Buchanan

Martin Foltin

Yoocharn Jeon

Cong Xu

Ben Feinberg

John Paul Strachan

Harumi Kuno

Amit S Sharma

Niladrish Chatterjee

Jishen Zhao

Anirban Nag

Han Bin Yoon

Benjamin Feinberg

Richard Stanley Williams

Raymond G Beausoleil

Ning Ge

Marco Fiorentino

Gary A Gibson

Melvin K Benedict

Mehul A Shah

Jeffrey Clifford Mogul

Vincent Hung Nguyen

Andrew Christopher Walton

Moray McLaren

Richard H Henze

Eric A Anderson

Miao Hu

Dhruva Ranjan Chakrabarti

Kevin T Lim

Chanh V Hua

Terence Patrick Kelly

Matteo Monchiero

John B Carter

Partha Ranganathan

James Ignowski

Liqun Cheng

Greg Astfalk

Hans Boehm

Jacquelyn M Ingemi

Doe-Hyun Yoon

Ali Shafiee-Ardestani

Parthasarathy Ranganthan

Karthik Ramani

Ali Ardestani

Pablo Faraboschi

Norm P Jouppi

While scheduled checkpoints are being taken of a cluster of active compute nodes distributively executing an application in parallel, a likelihood of failure of the active compute nodes is periodically and independently predicted. Responsive to the likelihood of failure of a given active compute node exceeding a threshold, the given active compute node is proactively migrated to a spare compute node of the cluster at a next scheduled checkpoint. Another spare compute node of the cluster can perform prediction and migration. Prediction can be based on both hardware events and software events regarding the active compute nodes.

Proactive cluster compute node migration at next checkpoint of cluster upon predicted node failure

In some examples, memristive dot product circuit based floating point computations may include ascertaining a matrix and a vector including floating point values, and partitioning the matrix into a plurality of sub-matrices according to a size of a plurality of memristive dot product circuits. For each sub-matrix of the plurality of sub-matrices, the floating point values may be converted to fixed point values. Based on the conversion and selected ones of the plurality of memristive dot product circuits, a dot product operation may be performed with respect to a sub-matrix and the vector. Each ones of the plurality of memristive dot product circuits may include rows including word line voltages corresponding to the floating point values of the vector, conductances corresponding to the floating point values of an associated sub-matrix, and columns that include bitline currents corresponding to dot products of the voltages and conductances.

Memristive dot product circuit based floating point computations

In an example, a method includes identifying, using at least one processor, data portions of a plurality of distinct data objects stored in at least one memory which are to be processed using the same logical operation. The method may further include identifying a representation of an operand stored in at least one memory, the operand being to provide the logical operation and providing a logical engine with the operand. The data portions may be stored in a plurality of input data buffers, wherein each of the input data buffers comprises a data portion of a different data object. The logical operation may be carried out on each of the data portions using the logical engine, and the outputs for each data portion may be stored in a plurality of output data buffers, wherein each of the outputs comprising data derived from a different data object.

Processing in-memory architectures for performing logical operations

Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.

Floating point data set compression

In an example, a method includes receiving, in a memory, input data to be processed in a first and a second processing layer. A processing operation of the second layer may be carried out on an output of a processing operation of the first processing layer. The method may further include assigning the input data to be processed according to at least one processing operation of the first layer, which may comprise using a resistive memory array, and buffering output data. It may be determined whether the buffered output data exceeds a threshold data amount to carry out at least one processing operation of the second layer and when it is determined that the buffered output data exceeds the threshold data amount, at least a portion of the buffered output data may be assigned to be processed according to a processing operation of the second layer.

Data processing using resistive memory arrays

Proactive cluster compute node migration at next checkpoint of cluster cluster upon predicted node failure

In an example, a method includes receiving input data and dividing the input data into a plurality of data portions, wherein the size of each data portion is based on a significance level. The input data may be assigned to at least one resistive memory array. Assigning the input data to at least one resistive memory array may comprises at least one of (i) assigning at least one data portion of the input data to be represented by a resistive memory array representing a number of bits, wherein the number of bits represented within the resistive memory array is based on the size of the at least one data portion; and (ii) processing each data portion of the input data with at least one resistive memory array.

Assigning data to a resistive memory array based on a significance level

In an example, a method comprises receiving a first matrix of values to be mapped to a resistive memory array, wherein each value in the matrix is to be represented as a resistance of a resistive memory element. An outlying value may be identified in the first matrix. At least one value of a portion of the first matrix containing the outlying value may be substituted with at least one substitute value to form a substituted first matrix.

Identifying outlying values in matrices

Example implementations of the present disclosure relate to in situ transposition of the data values in a memory array. An example system may include a non-volatile memory (NVM) array, including a plurality of NVM elements, usable in performance of computations. The example system may include an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements. The example system may further include a transposition engine to direct performance of the in situ transposition such that the plurality of data values remains stored by the original NVM elements.

In situ transposition

Examples disclosed herein include a dot product engine, which includes a resistive memory array to receive an input vector, perform a dot product operation on the input vector and a stored vector stored in the memory array, and output an analog signal representing a result of the dot product operation. The dot product engine includes a stored negation indicator to indicate whether elements of the stored vector have been negated, and a digital circuit to generate a digital dot product result value based on the analog signal and the stored negation indicator.

Dot product engine with negation indicator

Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.

Retrieve data block from determined devices

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

Smart memory buffers

Examples disclosed herein relate to a circuit having first and second analog processors and an analog-to-digital converter coupled to the first and second analog processors. The first analog processor provides a first analog signal having a voltage representing a function of a first vector and a second vector. The second analog processor provides a second analog signal having a voltage representing a function of a binary inverse of the first vector and the second vector. The analog-to-digital converter receives the first analog signal and the second analog signal, compares a signal selected from a group consisting of the first analog signal and the second analog signal to a reference voltage and based on the comparison to the reference voltage, determines a digital result representing the function of the first vector and the second vector.

Signal conversion based on complimentary analog signal pairs

A circuit includes an engine to compute analog multiplication results between vectors of a sub-matrix. An analog to digital converter (ADC) generates a digital value for the analog multiplication results computed by the engine. A shifter shifts the digital value of analog multiplication results a predetermined number of bits to generate a shifted result. An adder adds the shifted result to the digital value of a second multiplication result to generate a combined multiplication result.

Analog sub-matrix computing from input matrixes

Growing community of inventors

Santa Clara, CA, United States of America

Naveen Muralimanohar