Skhynix Inc.

Google Inc.

Intel Corporation

Sk Hynix Memory Solutions Inc.

Other

Nutanix, Inc.

Petaio Inc.

Seagate Technology Incorporated

Samsung Electronics Co., Ltd.

Applied Materials, Inc.

Naveen Kumar

Aman Bhatia

Fan Zhang

Chenrong Xiong

Yu Cai

Yi-Min Lin

Lingqi Zeng

Jason Bellorado

Zheng Wu

Johnson Yen

Thomas James Norrie

Xuanxuan Lu

Marcus Marrow

Shantanu R Gupta

Abhiram Prabhakar

Abhiram Prabahkar

Kyoung Lae Cho

Zeev Sperber

Ron Gabor

Nadav Bonen

Soo Jin Kim

Vjekoslav Svilan

David N Mackintosh

Jose A Baiocchi Paredes

Petros Maniatis

Jeffrey Adgate Dean

Erich Franz Haratsch

Quoc V Le

Binny Sher Gill

June Lee

Sunil Kumar

Bharat Kumar Beedu

Samuel Bengio

Azalia Mirhoseini

Sudish Kumar Sah

Mohammad Norouzi

Karthikeyan Subramaniam

Shuhei Tanakamaru

Rasmus Munk Larsen

Hieu Hy Pham

Benoit Steiner

Patrick Pannese

Ankush Jindal

Douglas MacLeod

Pranay Ega

Subramaniam V Iyer

Dharma Ratnam Srichurnam

Devendrappa Holeyannavar

Seok Lee

Kenneth Carpenter

Vivek R Rao

Yuefeng Zhou

Naveen Neelakantam

Niranjan Sanjiv Pendharkar

H Peter Anvin

Chung-Li Wang

David Pardo Keppel

Parthasarathy Ramachandran

Pranab Patnaik

David J Pignatelli

Frederick K H Lee

Karthik Chandrasekaran

Ranjan Parthasarathy

Kai Keung Chan

Arunkumar Subramanian

Sebastian Winkel

Shankar Gopalakrishna

Allan Douglas Knies

Franck Sala

Saju Cheeran Verghese Francis

Anil Koyad Choyikkunnil

Wei-Hao Yuan

Ganesh Sahukari

Bharath Kumar Beedu

Christopher S Tsang

Ori Lempel

Michael Neilly

HongChich Chou

Masha Lipshits

Lihu Rappaport

Nirajan L Cooray

Chengxu Zhang

An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Thused to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Thmay be calculated for each bit position. Thand the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

Bit flipping decoder using channel information

Iteration dependent bitwise bit flipping decoder

A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Data storage device

A computer-implemented method that includes monitoring execution of program code by first and second processor components. A computing system detects that a trigger condition is satisfied by: i) identifying an operand in a portion of the program code; or ii) determining that a current time of a clock of the computing system indicates a predefined time value. The operand and the predefined time value are used to initiate trace events. When the trigger condition is satisfied the system initiates trace events that generate trace data identifying respective hardware events occurring across the computing system. The system uses the trace data to generate a correlated set of trace data. The correlated trace data indicates a time ordered sequence of the respective hardware events. The system uses the correlated set of trace data to analyze performance of the executing program code.

Synchronous hardware event collection

A storage device includes 3D NAND including layers of multi-level cells. When a shutdown command is received, whether a block is partially written is evaluated. If so, dummy lines are written after the last written wordline of the block. Partially written blocks may be those having a fill percentage less than a threshold. The threshold may be a function of the PEC count of the block. If a maximum retention time is exceeded by data stored in a partially written block, dummy lines may also be written to the block.

Mitigating edge layer effect in partially written blocks

A method for determining a placement for machine learning model operations across multiple hardware devices is described. The method includes receiving data specifying a machine learning model to be placed for distributed processing on multiple hardware devices; generating, from the data, a sequence of operation embeddings, each operation embedding in the sequence characterizing respective operations necessary to perform the processing of the machine learning model; processing the sequence of operation embeddings using a placement recurrent neural network in accordance with first values of a plurality network parameters of the placement recurrent neural network to generate a network output that defines a placement of the operations characterized by the operation embeddings in the sequence across the plurality of devices; and scheduling the machine learning model for processing by the multiple hardware devices by placing the operations on the multiple devices according to the placement defined by the network output.

Device placement optimization with reinforcement learning

A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.

Distributed hardware tracing

Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells

A storage device includes 3D NAND including layers of multi-level cells. Test reads are performed by reading only LSB pages and reading layers in a repeating pattern of reading two and skipping two. A test read of a block is performed when its read count reaches a threshold. The counter threshold is updated according to errors detected during the test read such that the frequency of test reads increases with increase in errors detected. Counter thresholds according to errors may be specified in a table. The table may be selected as corresponding to a range of PEC values including the current PEC count of the 3D NAND. Each table further specifies a number of errors that will result in garbage collection being performed.

Adaptive read disturb algorithm for NAND storage accounting for layer-based effect

Methods, systems, and computer program products for moving a container-based application from a source HCl cluster to a target HCl cluster. An HCl storage cluster data replication mechanism operates to copy data and metadata from a plurality of storage devices that constitute a storage pool of the source HCl cluster. A container-based application replication mechanism operates to copy data and metadata from an executable container that is running on a node of the source HCl cluster. Periodically (1) the state of the container-based application is saved using the container-based application replication mechanism, and (2) the state of the storage cluster data of the HCl storage cluster is saved using the HCl storage cluster data replication mechanism. The saved state of the container-based application including its application data and metadata are combined with the saved state of the storage cluster data to bring-up the container-based application at the target HCl cluster.

Container-based application processing

A system includes a mobile device having one or more cameras to take images; a sensor detecting reflected light from one or more lasers and a diffuser to detect object range or dimension; code for motion tracking, environmental understanding by detecting planes in an environment, and estimating light and dimensions of the surrounding based on the one or more lasers; code to estimate a three-dimensional (3D) volume of an object from multiple perspectives and from projected laser beams to measure size or scale and determine locations of points on the object's surface in a plane or a slice using time-of-flight, wherein positions and cross-sections for different slices are correlated to construct a 3D model of the object, including object position and shape; the device receiving user request to select a content from one or more augmented, virtual, or extended reality contents and rendering a reality view of the environment.

Systems and methods for computer assisted operation

Systems and methods for unified application-level backup and restore using heterogeneous cloud-based backup service providers. An application programming interface is configured to process both data level replication operations as well as application-level operations that are executed to carry out high-level commands between a virtualized computing environment and any one or more of the heterogeneous cloud-based backup service providers. The API receives commands from applications in the virtualized computing environment. The API processes commands from the applications so as to facilitate replication of data to selected one or more cloud-based backup service providers. The commands perform data level replication operations as well as application-level operations for storing content to the cloud-based service provider. After a failure event and/or upon receipt of a restore command, the API initiates application-level operations that restore the application and its constituent entities. The data state is restored by the API using data level restore operations.

Context-based disaster recovery

Provided is a method for optimizing radio resource for Ultra-Reliable Low Latency Communication services in a Dual Connectivity technology. The method includes: receiving DownLink (DL) data by a UE using a first Radio Access Technology (RAT) from a base station; transmitting a first Acknowledgement (ACK) signal using the first RAT to the base station based on the DL data being successfully received; updating a Mapping Table Sequence Number of the DL data in a Mapping Table by the UE, based on the DL data being successfully received by the UE using the first RAT; checking the Mapping Table by the UE upon detecting an error in the received DL data using a second RAT; and sending a second ACK signal to the base station using the second RAT of the UE based on the Mapping Table Sequence Number of the DL data being found in the Mapping Table.

Method and user equipment apparatus for optimizing radio resource for URLLC services in dual connectivity technology

Growing community of inventors

San Jose, CA, United States of America

Naveen Kumar