International Business Machines Corporation

Globalfoundries Inc.

Natalie Barbara Feilchenfeld

Michael Joseph Zierak

Yun Shi

Benjamin T Voegeli

Qizhi Liu

Zhong-Xiang He

Jeffrey P Gambino

Steven H Voldman

Richard A Phelps

Santosh Sharma

Douglas Duane Coolbaugh

Ebenezer E Eshun

Theodore James Letavic

Max Gerald Levy

Stephen Joseph Fuerniss

Vibhor Jain

Xuefeng Liu

John Steven Kresge

James Warren Wilson

Bradley Alan Orner

BethAnn Rainey

Frederick Gustav Anderson

Scott Preston Moore

Ronald P Nowak

Michael Lawrence Gautsch

BethAnn Lawrence

Ping-Chuan Wang

Michael A Gaynes

James William Adkisson

William Louis Brodsky

Mark Vincent Pierson

James Albert Slinkman

David Brian Stone

Donald Seton Farquhar

James Stuart Dunn

Vidhya Ramachandran

Andreas Daniel Stricker

James Robert Wilcox

Lisa Jeanine Jimarez

David L Harmon

Kimball M Watson

Michael Wozniak

Ronald Jay Bolam

Matthew D Moon

Keith Edward Downes

Barbara Ann Waterhouse

Pat Hoontrakul

Anthony K Stamper

Voya Rista Markovich

Hanyi Ding

Robert Mark Rassel

Frank Daniel Egitto

Renata A Camillo-Castillo

Howard Smith Landis

William E Wilson

Stephen Arthur St Onge

Louis DeWolf Lanzerotti

David S Collins

Elizabeth F Foster

Yves T Ngu

William T Chen

Christina Marie Boyko

Paul George Rickerl

Martin Knaipp

Rainer Minixhofer

Georg Roehrer

Ernest Bassous

Hubert Enichlmair

James Steven Kamperman

Michael R Scheuermann

Gobinda Das

Brennan J Brown

John J Benoit

Walter P Pawlowski

John J Glenning

Yifan Guo

Douglas H Strope

Giana M Phelan

Donald J Mikalsen

Kathleen Lorraine Covert

Stanley M Albrechta

Paul Gerard Wilkin

Bernard Loeffler

Jong-Mun Park

George Dean Ogden

John Andrejack

Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p-and n-terminals formed in an i-region above a substrate.

Lateral PiN diodes and schottky diodes

Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer

Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.

Tapered gate oxide in LDMOS devices

Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.

Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A contact trench is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate to a buried oxide layer of the SOI substrate. An isolation trench is formed that extends through the device layer to the buried oxide layer. An electrical insulator is deposited that fills the contact trench and the first isolation trench. The electrical insulator is removed from the contact trench. After the electrical insulator is removed from the contact trench, an electrical conductor is formed in the contact trench. The electrical contact may be coupled with a doped region in a handle wafer of the SOI substrate.

Structures with contact trenches and isolation trenches

Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.

Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure

A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.

Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method

Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Dual shallow trench isolation (STI) structure for field effect transistor (FET)

A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The method includes substantially simultaneously forming a first opening and a second opening extending from the semiconductor layer to the conductive region; introducing an insulating material to the side walls of the first opening; at least partially filling the first opening with a semiconductor material to provide an ohmic contact trench; and at least partially filling the second opening with an insulating material to form a device isolation trench. Insulating regions, for example, shallow trench isolation (STI) regions, may be formed about the device isolation trench and the ohmic contact trench. Semiconductor structures are also provided. The benefits of combining the features of SOI and STI structures are provided.

A collector region is formed between insulating shallow trench isolation regions within a substrate. A base material is epitaxially grown on the collector region and the shallow trench isolation regions. The base material forms a base region on the collector region and extrinsic base regions on the shallow trench isolation regions. Further, a sacrificial emitter structure is patterned on the base region and sidewall spacers are formed on the sacrificial emitter structure. Planar raised base structures are epitaxially grown on the base region and the extrinsic base regions, and the upper layer of the raised base structures is oxidized. The sacrificial emitter structure is removed to leave an open space between the sidewall spacers and an emitter is formed within the open space between the sidewall spacers. The upper layer of the raised base structures comprises a planar insulator electrically insulating the emitter from the raised base structures.

Self-aligned bipolar junction transistor having self-planarizing isolation raised base structures

High-voltage LDMOS devices with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming an insulator layer of varying depth over a drift region and a body of a substrate. The method further includes forming a control gate and a split gate region by patterning a layer of material on the insulator layer. The split gate region is formed on a first portion of the insulator layer and the control gate is formed on a second portion of the insulator layer, which is thinner than the first portion.

High voltage laterally diffused metal oxide semiconductor

A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.

Lateral diffusion field effect transistor with drain region self-aligned to gate electrode

Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (T) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (V) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.

Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance

Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (V) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vof the diode (e.g., increasing the length reduces Vof the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.

Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode

Growing community of inventors

Jericho, VT, United States of America

Natalie Barbara Feilchenfeld