Megachips Corporation

Naotsugu Yamamura

Akira Okamoto

Makoto Saito

Nobuyuki Takasu

Takuya Hiraoka

In an earliest vertical synchronization period after sending an encoded image data is restarted, a first reference image determination circuit determines to employ a local decoded image generated in a vertical synchronization period immediately preceding a vertical synchronization period in which an error occurs among multiple local decoded images stored in a first DRAM as a reference image. In an earliest vertical synchronization period after a decoding circuit is reset, a second reference image determination circuit determines to employ a decoded image generated in the vertical synchronization period immediately preceding the vertical synchronization period in which the error occurs among multiple decoded images stored in a second DRAM as a reference image.

Image processor

In an image coding apparatus (), a Hadamard transform unit () performs horizontal Hadamard transform on a picture of uncompressed image data (). The sum total of absolute values of AC component values obtained by the Hadamard transform is calculated as a Hadamard value () of the picture. A scene change determination unit () determines whether a scene change occurs or not in the picture on the basis of the Hadamard value (). In a case where a scene change occurs in the picture or where a differential absolute value between the amount of generated codes in a coded GOP and the ideal amount of codes in a GOP is larger than a predetermined reference value, a quantization parameter determination unit () determines a quantization parameter () of the picture on the basis of the Hadamard value () and the target amount of codes of the picture. A coding unit () codes the picture by using the determined quantization parameter ().

Image coding apparatus

Each second selection circuit selects, out of a plurality of evaluation values, an evaluation value being in a predetermined relative positional relation with a first evaluation value as an evaluation value outputted from a first selection circuit, and outputs the selected value. The predetermined relative positional relations are different from one another among a plurality of second selection circuits. Every time a second evaluation value is outputted from the second selection circuit corresponding to the integration circuit, the integration circuit reads a weigh value corresponding to a combination of the second evaluation value and the first evaluation, which makes a pair with the second evaluation and is outputted from the first selection circuit, from a storage circuit corresponding to the second selection circuit and integrates the read values. An addition circuit at least adds a plurality of integrated values outputted from a plurality of integration circuits, and an addition value obtained thereby becomes a probability value.

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Osaka, Japan

Naotsugu Yamamura