Applied Materials, Inc.

University of California

Varian Semiconductor Equipment Associates, Inc.

Naomi Yoshida

Shiyu Sun

Lin Dong

Yixiong Yang

Bingxi Sun Wood

Benjamin Colombeau

Shih Chung Chen

Nam Sung Kim

Michael Patrick Chudzik

Wei V Tang

Seshadri Ganguli

Yuichi Wada

Theresa Kramer Guarini

Sung Won Jun

Hiroyuki Yarita

Paul F Ma

He Ren

Andrew C Kummel

Jacqueline S Wrench

Adam Brand

Hisashi Aida

Vanessa Pena

Mei Yin Chang

David P Thompson

Srinivas Gandikota

Mehul B Naik

Errol Antonio C Sanchez

Sang Ho Yu

Steven C H Hung

Liqi Wu

Jessica Sevanne Kachian

Yongjing Lin

Wenyu Zhang

Sheng-Chin Kung

Chi-Chou Lin

Karla M Bernal Ramos

Mary Edmonds

Miao Jin

Feng Quan Liu

Deenesh Padhi

Siddarth A Krishnan

Bok Hoen Kim

Jeffrey W Anthis

Yu Lei

Jingmei Liang

Martin Jay Seamons

Mei-Yee Shek

Yi Xu

Hans-Joachim Ludwig Gossmann

Nikolaos Bekiaris

Hang Yu

Atashi Basu

Sohyun Park

Heung Lak Park

Shahid Shaikh

Siu Fai Cheng

Li Yan Miao

Luping Li

Shi You

Sang Wook Park

Man-Ping Cai

Toshiyuki Nagata

Chenfei Shen

Hyunwoong Kim

Nitin K Ingle

Wei Liu

Rongjun Wang

Mikhail Korolik

Mandyam Sriram

Xikun Wang

Yihwan Kim

Hao Chen

Wen Xiao Chen

Shariq Siddiqui

Sang-Ho Yu

Rajesh Sathiyanarayanan

Mandar Balasaheb Pandit

David Michael Thompson

Xuesong Lu

Hao Jiang

Steven C Hung

Dimitri R Kioussis

Myungsun Kim

Soumendra N Barman

Tobin Kaufman-Osborn

Srividya Natarajan

Bhagawan Sahu

Kasra Sardashti

Ilanit Fisher

Chi-Nung Ni

Drew Phillips

Tyler Kent

Kedi Wu

Steve Wolf

Gaetano Santoro

Chen-Han Lin

Kaliappan Muthukumar

Hisashl Aida

Chen Han Lin

Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.

Fluorine-free tungsten ALD for dielectric selectivity improvement

Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.

Method of dielectric material fill and treatment

Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200° C. by using an organic platinum group metal precursor.

Electronic device having an oxygen free platinum group metal film

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitriride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).

Integrated dipole flow for transistor

Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.

Horizontal gate-all-around device nanowire air gap spacer formation

Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

Method of cleaning a structure and method of depositing a capping layer in a structure

Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200&#xb0; C. by using an organic platinum group metal precursor.

Oxygen free deposition of platinum group metal films

Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.

Horizontal gate all around device nanowire air gap spacer formation

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-&#x3ba; dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Horizontal gate all around and FinFET device isolation

Methods and apparatus for forming a semiconductor structure such as an NMOS gate electrode are described. Methods may include depositing a first capping layer having a first surface atop a first surface of a high-k dielectric layer; and depositing at least one metal layer having a first surface atop the first surface of the first capping layer, wherein the at least one metal layer includes titanium aluminum silicide material. Some methods include removing an oxide layer from the first surface of the first capping layer by contacting the first capping layer with metal chloride in an amount sufficient to remove an oxide layer. Some methods for depositing a titanium aluminum silicide material are performed by an atomic layer deposition process performed at a temperature of 350 to 400 degrees Celsius.

Methods and apparatus for n-type metal oxide semiconductor (NMOS) metal gate materials using atomic layer deposition (ALD) processes with metal based precursors

The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.

Methods are described herein for etching tantalum-containing films with various potential additives while still retaining other desirable patterned substrate portions. The methods include exposing a tantalum-containing film to a chlorine-containing precursor (e.g. Cl) with a concurrent plasma. The plasma-excited chlorine-containing precursor selectively etches the tantalum-containing film and other industrially-desirable additives. Chlorine is then removed from the substrate processing region. A hydrogen-containing precursor (e.g. H) is delivered to the substrate processing region (also with plasma excitation) to produce a relatively even and residue-free tantalum-containing surface. The methods presented remove tantalum while retaining materials elsewhere on the patterned substrate.

Tantalum-containing material removal

Methods and apparatus for forming a semiconductor structure, including depositing a doping stack having a first surface atop a high-k dielectric layer, wherein the doping stack includes at least one first metal layer having a first surface, at least one second metal layer comprising a first aluminum dopant and a first surface, wherein the second metal layer is atop the first surface of the first metal layer, and at least one third metal layer atop the first surface of the second metal layer; depositing an anneal layer atop the first surface of the doping stack; annealing the structure to diffuse at least the first aluminum dopant into the high-k dielectric layer; removing the anneal layer; and depositing at least one work function layer atop the first surface of the doping stack.

Methods and apparatus for doping engineering and threshold voltage tuning by integrated deposition of titanium nitride and aluminum films

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Sunnyvale, CA, United States of America

Naomi Yoshida