Mitsubishi Denki Kabushiki Kaisha

Naoko Otani

Toshiharu Katayama

Yukari Imai

Katsuhiko Tamura

Each of source regions (4) is provided only immediately below a bottom surface (3B) of each of trenches (3) which is formed in a silicon substrate (1), extending inward from a main surface (1S) thereof along a second direction, and each of gate electrode portions (23) is provided inside each of the trenches (3). Specifically, each of the gate electrode portions (23) consists of a gate oxide film (19) formed on a side surface (S1) and part of the bottom surface (3B) of the trench (3), an FG electrode (20) formed thereon, a gate insulating film (21) formed on a side surface of the FG electrode (20) which is out of contact with the gate oxide film (19), an upper surface of the FG electrode (20), a side surface (2S) and the other part of the bottom (3B) of the trench (3), and a CG electrode (22) formed so as to cover an upper surface of the gate insulating film (21). Each of drain regions (11) is shared by the two adjacent transistors. The device configuration as above achieves reduction in area of the gate electrode portions (23) and further reduction in each level difference between both regions having and not having the gate electrode portion (23). Thus, reduction in level difference of each memory cell is achieved while reduction in area of each memory cell is ensured.

Semiconductor device comprising trench EEPROM

A non-volatile semiconductor storage device with which a multi-value memory is realized and the amount of information storable is increased without increasing the number of memory transistors and the area occupied thereby. A gate electrode portion 20a of each memory transistor has a two-layer floating gate structure comprising two floating gate electrodes 22a, 22b and a control gate electrode 24 which are substantially vertically laminated one above another. The non-volatile semiconductor storage device is thereby constructed as a multi-value memory capable of providing a state '1' where electrons are injected into the first floating gate electrode 22a, a state '0' where electrons are injected into the first and second floating gate electrodes 22a, 22b, and a state '2' where electrons are withdrawn from the first and second floating gate electrodes 22a, 22b.

Non-volatile semiconductor information storage device

A semiconductor device (100) including a silicon substrate (1), a gate oxide film (2) formed on the silicon substrate (1) and having a defect (3) and a dielectric breakdown voltage failure portion (4), and a polysilicon film (5) formed on the gate oxide film (2) is immersed in a chemical etchant (7) in a wet etching apparatus (9). With the silicon substrate (1) serving as an anode, a DC voltage source (6) of the wet etching apparatus (9) applies voltage to the silicon substrate (1) to perform anode oxidation. Passivation layers (10) are formed on parts of the surface of the polysilicon film (5) which overlies the defect (3) and dielectric breakdown voltage failure portion (4) but are not formed on the surface of the polysilicon film (5) in regions insulated by the gate oxide film (2). The polysilicon film (5) in the regions on which the passivation layers (10) are not formed is removed by the chemical etchant (7).

Method of evaluating a thin film for use in semiconductor device

A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.

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Tokyo, Japan

Naoko Otani