Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Other

Naoki Yutani

Kenichi Ohtsuka

Hiroshi Watanabe

Kenichi Kuroda

Kazuhiko Tsutsumi

Naruhisa Miura

Yoichiro Tarui

Masayuki Imaizumi

Yoshinori Matsuno

Hiroshi Ohji

Shuhei Nakata

Masafumi Kimata

Shoyu Watanabe

Shozo Shikama

Katsumi Suzuki

Shiro Hino

Youichi Enomoto

Yoshiyuki Nakaki

Hidekazu Yamamoto

Eisuke Suekawa

Masashi Ueno

Yuichi Sakai

Masahiko Denda

Yuji Ebiike

Shiro Hine

Yasunori Oritsuki

Hiroaki Sumitani

Jian-Guo Wen

Daisuke Chikamori

Sotoju Asai

Satoshi Hirose

Yasuhiko Nishio

Provided is a semiconductor device including an active region provided in a first conductivity type semiconductor layer and a termination region provided around the active region. A MOS transistor through which a main current flows in a thickness direction of the semiconductor layer is formed in the active region. The termination region includes a defect detection device provided along the active region. The defect detection device includes a diode including a first main electrode provided along the active region on a first main surface of the semiconductor layer, and a second main electrode provided on a second main surface side of the semiconductor layer.

Semiconductor device and method of manufacturing the same

A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V.

Method of manufacturing silicon carbide semiconductor device

In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side of the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first well, the second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.

Semiconductor device and method for manufacturing the same

It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.

Silicon carbide semiconductor device and method of manufacturing the same

A silicon carbide semiconductor device includes: a drift layer of the a first conduction type; a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer; a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; and a surface electrode pad on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode.

Silicon carbide semiconductor device

In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.

A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C&#xb7;K/(N+1).

Epitaxial wafer and semiconductor element

A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n-type semiconductor layer. The anode electrode forms a Schottky junction with the n-type semiconductor layer and forms an ohmic junction with the p-type contact layer.

Semiconductor device including a cell array having first cells and second cells interspersed around the arrangement of the first cells

An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.

An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer; (c) removing a surface layer of the silicon carbide layer, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.

Method for manufacturing silicon carbide semiconductor device

An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400&#xb0; C. to 600&#xb0; C. to form a Schottky junction of desired characteristics between the second metal layer and the epitaxial layer.

In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an ntype semiconductor layer formed on an ntype semiconductor substrate; a first electrode that is formed on the ntype semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the ntype semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in a surface of the ntype semiconductor layer; an insulating film provided so as to cover the GR layer and the JTE layer; and a second electrode that is an Ohmic electrode formed below a rear surface of the ntype semiconductor substrate.

Semiconductor device having a groove and a junction termination extension layer surrounding a guard ring layer

A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode unitsis formed on an SiC chip, and each of the unitshas an external output electrodeindependently of each other. Bumps(the diameter is from several tens to several hundreds of &#x3bc;m) are formed only on the external output electrodesof non-defective units among the unitsformed on the SiC chip, meanwhile bumps are not formed on the external output electrodesof defective units in which the withstand voltage is too low, or the leakage current is too much. Because the bumps are not formed on the defective units, Schottky-barrier-side electrodesare connected in parallel to the exterior of the device through the bumps, and a wiring layerand an external leadof a wiring substrate; thus, only the external output electrodesof the non-defective unitsare connected in parallel with each other.

Semiconductor device and manufacturing method therefor

A pressure sensor includes a first diaphragm having a first surface receiving pressure, a first thermal detection section located opposite a central section of the first diaphragm, and a second thermal detection section having little displacement by pressure, and located opposite the first diaphragm The pressure sensor amplifies and outputs a difference between the first thermal detection section for pressure measurement and the second thermal detection section for reference output. Since the diaphragm to which the second thermal detection section is opposed is equal in thickness to the diaphragm to which the first thermal detection section is opposed, pressure can be accurately measured relative to a sudden change in atmospheric temperature.

Growing community of inventors

Tokyo, Japan

Naoki Yutani