Nec Corporation

Nec Electronics Corporation

Tokyo Seimitsu Co., Ltd.

Naoki Kasai

Toru Tatsumi

Hiromitsu Hada

Hiroki Koga

Hidemitsu Mori

Hiroshi Watanabe

Akira Yamaguchi

Shunsuke Fukami

Takashi Sakoh

Toshihiro Iizuka

Takehiko Hamada

Hiroki Ishida

Yasuhito Iguchi

Yuta Sato

Wataru Kawasaki

Teppei Aoki

Kazuma Takii

Naoyuki Yamazoe

Tetsuya Yasunaka

The wafer test system includes: a prober including a chuck that holds a semiconductor wafer and a probe card having probe needles thereon, and brings the probe needles in contact with semiconductor chips formed on the semiconductor wafer to inspect the semiconductor chips; an overhead hoist transport that delivers the cassette that houses the plurality of semiconductor wafers to be inspected to the prober and withdraws, from the prober, the cassette that houses the semiconductor wafers that have been inspected; a conveying control unit that controls the overhead hoist transport to convey the probe card between a replacement position of the probe card predetermined in the prober and a storage of the probe card located in a place different from the prober; and a card conveying mechanism that conveys the probe card between a holding position in the prober and the replacement position.

Wafer test system, probe card replacing method, and prober

An MRAM according to the present invention is provided with a magnetic recording layer being a ferromagnetic layer and a pinned layer connected to the magnetic recording layer through a nonmagnetic layer. The magnetic recording layer includes a magnetization switching region, a first magnetization fixed region and a second magnetization fixed region. The magnetization switching region has reversible magnetization and overlaps with the pinned layer. The first magnetization fixed region and the second magnetization fixed region are both connected to the same one end of the magnetization switching region. Also, the first magnetization fixed region and the second magnetization fixed region respectively have first fixed magnetization and second fixed magnetization whose directions are fixed. One of the first fixed magnetization and the second fixed magnetization is fixed in a direction toward the above-mentioned one end, and the other is fixed in a direction away from the above-mentioned one end.

MRAM and data read/write method for MRAM

In a method of manufacturing a semiconductor memory device, a lower electrode film is formed on a semiconductor substrate via an interlayer insulating film. A ferroelectric film is formed on the lower electrode layer while heating the lower electrode layer uniformly in the cell array region. An upper electrode film is formed on the ferroelectric film. Ferroelectric capacitors are formed in a memory cell array region. Each of the ferroelectric capacitors includes the lower electrode film, the ferroelectric film and the upper electrode film.

Semiconductor memory device with memory cells having same characteristics and manufacturing method for the same

It is a purpose of the invention to provide a semiconductor device comprising a high density integrated circuit having a large number of insulated gate field effect transistors having minute size and improved performance and uniformity. The source contact resistance is set in a value smaller than that of the drain contact resistance by making the diameter of a source contact of an insulated gate field effect transistor larger than that of the drain contact, so as to improve the current driving capability of the transistor and to reduce the variation in the capability.

Semiconductor device comprising high density integrated circuit having a large number of insulated gate field effect transistors

An embedded LSI includes a FeRAM macro block and an associated logic circuit section. A hydrogen barrier layer covers the FeRAM macro block as a whole and exposes the logic circuit section. The edge of the hydrogen barrier layer overlies the peripheral circuit of the FeRAM macro block and the boundary separating the FeRAM macro block from the logic circuit section. The ferroelectric capacitor is protected by the hydrogen barrier layer against hydrogen during a hydrogen-annealing process.

Embedded LSI having a FeRAM section and a logic circuit section

A DRAM includes a MOSFET and a stacked capacitor in each memory cell. The stacked capacitor includes a bottom electrode substantially of a cylindrical shape, a top electrode received in the cylindrical-shape bottom electrode, and a capacitor dielectric film for insulation therebetween. The cylindrical shape of the bottom electrode allows a larger deviation for alignment between the capacitor and the capacitor contact.

DRAM having a stacked capacitor and a method for fabricating the same

The method of manufacturing a semiconductor device having a first and second semiconductor element formation regions. The second gate electrode is of a second semiconductor element formation region while the first semiconductor element formation region is masked. The second source/drain region is a of the second semiconductor element and is formed in the second semiconductor element formation region while the first semiconductor element formation region is masked. The second sidewall insulating film are formed on side portions of the second gate electrode while the first semiconductor element formation regions is masked. The first gate electrode is of a first semiconductor element and is formed in the first semiconductor element formation region while the second semiconductor element formation region is masked. The first source/drain region is of the first semiconductor element and is formed in the first semiconductor element formation region while the second semiconductor element formation region is masked. The first sidewall insulating films is formed on side portions of the first gate electrode.

Method of manufacturing semiconductor device in which hot carrier resistance can be improved and silicide layer can be formed with high reliability

The present invention also provides a multilevel interconnection structure comprising: at least a set of a first lower level contact plug extending in a lower level inter-layer insulator structure and a first higher level contact plug extending in a higher level inter-layer insulator structure extending over the lower level inter-layer insulator structure, wherein a top of the first lower level contact plug is contact directly with a bottom of the first higher level contact plug without intervening any interconnection pad; a stopper insulating film extending between the lower level inter-layer insulator structure and the higher level inter-layer insulator structure; and at least a lower-level single conductive united structure which further comprises: a second lower level contact plug extending in the lower level inter-layer insulator structure; and a first lower level interconnection extending in a lower-level interconnection groove formed in an upper region of the lower level inter-layer insulator structure, wherein a top surface of the first lower level interconnection is leveled to a top surface of the lower level inter-layer insulator structure and also leveled to the top of the first lower level contact plug.

Semiconductor device with reduced number of intermediate level interconnection pattern and method of forming the same

A device for capacitor characteristic evaluation is provided, which enables measurement of the characteristic of a capacitor immediately after the completion of its formation processes, and which improves the fabrication yield. This device is comprised of (a) a conductive region formed on a semiconductor substrate; (b) an interlayer dielectric layer formed to cover the conductive layer; (c) a first electrode formed on the interlayer dielectric layer; (d) a second electrode formed on the interlayer dielectric layer to be apart from the first electrode; the second electrode being electrically connected to the first electrode through the conductive region; (e) a capacitor dielectric formed to cover the first and second electrodes; the capacitor dielectric being contacted with the first and second electrodes; (f) a third electrode formed on the capacitor dielectric to be opposite to the first electrode via the capacitor dielectric; (g) a fourth electrode formed on the capacitor dielectric to be apart from the third electrode to be opposite to the second electrode via the capacitor dielectric; (h) the first electrode, capacitor dielectric, and third electrode constitute a first capacitor and the second electrode, capacitor dielectric, and fourth electrode constitute a second capacitor; and (i) the third and fourth electrodes constitute a pair of measuring terminals.

Characteristic-evaluating storage capacitors

A semiconductor device that enables to avoid short-circuit between an interconnection film and an underlying conductive region even when a contact hole is partially overlapped with an isolation insulator. A conductive region is selectively formed in an active region to be contacted therewith. An interlayer insulating film having a contact hole is formed to cover the active region and the isolation insulator. An interconnection film is formed on the interlayer insulator film to be contacted with the conductive region through the contact hole. The isolation region contains a first insulating subregion and a second insulating subregion formed on the first insulating subregion. The first insulating subregion is positioned at a deeper level than that of the second insulating subregion. The second insulating subregion may be formed in self-alignment to the first insulating subregion and may have a substantially flat surface. A part of the second insulating subregion is exposed in the contact hole so that the contact area of the interconnection film with the conductive region is partially defined by the isolation region.

Semiconductor device and fabrication method thereof

A gate electrode,is provided on a surface of a semiconductor substrate,, an insulation film,being formed over the gate electrode,and the side wall of the gate electrode,being covered by an insulation film,, and, on a diffusion region,that is formed on the surface of the semiconductor substrate,at both sides of the above-noted gate electrode,and in a region that is sandwiched between the above-noted side walls,, a silicon single crystal is anisotropically grown in a direction that is perpendicular with respect to the semiconductor substrate,, so as to form a pad,, and the anisotropic growth of the silicon single crystal is only within a part,of the region sandwiched between parts of the side wall,that are perpendicular to the substrate surface.

Semiconductor device and method for manufacturing same

A semiconductor device includes a first diffusion layer, an insulating film, and an electrode. The first diffusion layer is formed on the surface of a first-conductivity-type semiconductor substrate and has an opposite conductivity type. The insulating film is formed on the first diffusion layer. The electrode is made of a conductor layer formed on the insulating film. The width of the electrode is smaller than a value twice the length by which an impurity doped into the surface of the semiconductor substrate, using the electrode as a mask, laterally diffuses during annealing to a position immediately below the electrode.

MOS semiconductor device and method of manufacturing the same

A semiconductor dynamic random access memory device includes plural memory cell arrays arranged in two columns, and the memory cell arrays of one column has memory cell sub-arrays and peripheral circuits such as sense amplifiers and sub-word line drivers arranged around the memory cell sub-arrays; the memory cells of the sub-arrays are arranged in a first pattern, and the peripheral circuits of adjacent sub-arrays are arranged in symmetry with respect to a line of symmetry perpendicular to the direction of the columns so as to increase a margin of alignment without sacrifice of simplicity of design work.

Semiconductor memory device having memory cells similarly layouted and

On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug. As a result, increase in leakage at the junction of the diffusion layer is prevented by the low-resistance contact plug including the silicon-germanium alloy.

Growing community of inventors

Tokyo, Japan

Naoki Kasai