Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Toshiba America Electronic Components, Inc.

Siemens Microelectronics Limited

Naohiro Shoda

Peter Weigand

Katsuya Okumura

A wafer processing apparatus includes a processing chamber, a chuck arranged in the processing chamber for supporting a wafer, and a pedestal which is spaced apart from the chuck. A first gas layer is provided between the chuck and the wafer and a second gas layer is provided in the space between the pedestal and the chuck. The pressure of the first gas layer is controlled to be in a pressure range in which a thermal conductivity of the first gas layer is substantially constant with respect to changes in pressure of the first gas layer and the pressure of the second gas layer is controlled so as to control an amount of heat transferred to/from the pedestal.

Semiconductor workpiece processing apparatus and method

A method for fabricating a shallow trench isolation structure involves several steps. The steps of an illustrative method include forming a first resist pattern on a substrate, etching the substrate to form a shallow trench therein using the first resist pattern as a mask, removing the first resist pattern from the substrate, depositing an oxide layer on the substrate including in the shallow trench, depositing a polish stop layer on the oxide layer, forming a second resist pattern on a portion of the polish stop layer substantially covering the shallow trench using the same mask as the mask for the first resist pattern, etching the polish stop layer, removing the second resist pattern leaving the portion of the polish stop layer substantially covering the shallow trench, polishing the oxide layer using the portion of the polish stop layer substantially covering the shallow trench as a polish stop, and removing the portion of the polish stop layer substantially covering the shallow trench.

Method of manufacturing a shallow trench isolation structure for a

Apparatus and method are provided for obtaining improved measurement and control of the temperature of a semiconductor wafer (W) during processing. The apparatus includes a chuck for holding a wafer during processing, a coolant gas supply (16), and a temperature sensing arrangement for measuring and controlling the temperature of the wafer during processing. A top face of the chuck (22) over which the wafer is positioned, is configured with a plurality of holes (34) into which the coolant gas, such as helium, is admitted at controlled rate and pressure. The coolant gas passes through a narrow space (36) between the top face of the chuck and the underside of the wafer and is evacuated via an exhaust line (30) after being heated to (or nearly to) the temperature of the wafer. Temperature of the now-heated coolant gas is continuously measured by a temperature sensor arrangement which generates a signal controlling the pressure and flow of coolant gas to the wafer. Close control of the temperature of the wafer is thereby maintained continuously at a desired value during processing.

Semiconductor wafer temperature measurement and control thereof using

A method for fabricating a damascene interconnect includes the steps of depositing a metal layer of the surface of an insulating film; etching the metal layer and the insulating film to form an insulating groove; depositing a silicon layer on an upper surface on the metal layer and on each sidewall and a bottom of the insulating groove; annealing the silicon layer and the metal layer to form a silicide layer; implanting ions in the bottom of the insulating groove; and depositing an interconnect material in the insulating groove using selective chemical vapor deposition. In one embodiment, the metal layer is a titanium layer, the interconnect material is tungsten, and the implanted ions are arsenic ions.

Method of forming an interconnect

A method of manufacturing a semiconductor device having a stud and interconnect in a dual damascene structure uses selective deposition. The method includes forming a trench including a first opening portion and a second opening portion in a dielectric layer, forming a first adhesion layer on a surface exposed by the first opening portion, forming a second adhesion layer on a surface exposed by the second opening portion, and selectively depositing a conductive material on the first adhesion layer and the second adhesion layer, wherein growth of the conductive material on the second adhesion layer starts after growth of the conductive material on the first adhesion layer has started. The first and second adhesion layers are of different materials.

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Wappingers Falls, NY, United States of America

Naohiro Shoda