Nippon Telegraph and Telephone Public Corporation

Takeda Riken Kogyo Kabushiki Kaisha

Takeca Riken Kogyo Kabushiki Kaisha

Naoaki Narumi

Kohji Ishikawa

Masao Shimizu

Kenji Kimura

Takashi Tokuno

Osamu Ohguchi

Shigeru Sugamori

Hiromi Maruyama

A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.

Semiconductor memory device test apparatus

A semiconductor memory test equipment which reads out a memory under test by an address from a pattern generator and compares the read-out data with an expected value by a comparator, and in which a block mask memory is read out by a portion of the address and the comparing operation of the comparator is inhibited by block mask data read out from the block mask memory. Pattern data for a pattern memory, which is read out by the abovesaid address to store data to be supplied to the comparator, are transferred as parallel data from a central processor and written in the pattern memory after conversion to serial data, and serial data read out from a defective address memory are inputted to the central processor after conversion to parallel data.

Semiconductor memory test equipment

An address pattern generator for use in a test pattern generator for generating various patterns for testing semiconductor memories. A plurality of fixed registers for storing an initial value at the start of a test, a boundary value and an operand indicating the amount of change of an address are provided in common to at least two address operating circuits. The address operating circuits are each capable of taking therein the content of a desired one of the fixed registers. At least two output registers are provided, which are each capable of taking therein the operation result of a desired one of the address operating circuit. The contents of these output registers are supplied as addresses to a memory under test.

Address pattern generator for testing a memory

A test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory control signal being applied to a memory under test. The address pattern is provided to an area inversion control signal generation section to produce an inversion control signal corresponding to the address pattern, by which the data pattern may be inverted and then outputted.

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Tokyo, Japan

Naoaki Narumi