Mosel Vitelic Corporation

Nan-Hsiung Tsai

Min-Liang Chen

A dynamic random access memory (DRAM) integrated circuit (,). The DRAM (,) includes a recessed region (,) defined in a semiconductor substrate (,). This recessed region has substantially vertical sides (,) extending from a bottom surface (,). A field effect transistor (,) is defined adjacent to the recessed region (,). A capacitor structure, including a lower capacitor plate (,), a capacitor dielectric (,), and an upper capacitor plate (,), is defined in the recessed region (,) and over the field effect transistor (,), thereby providing a greater capacitor surface.

High density memory structure

A method and structure for a lower capacitor electrode for a dynamic random access integrated circuit. A polysilicon gate layer is formed over a thin layer of oxide in a first region of a semiconductor substrate. Another oxide layer is then formed overlying the polysilicon gate layer. A polysilicon layer which was doped by S/D implant including the lower capacitor electrode self-aligns and forms overlying a second region of the semiconductor substrate and over the oxide layer on the polysilicon gate layer. A nitride layer forms on the lower capacitor electrode portion overlying the second region. Exposed portions of the polysilicon layer are then oxidized. The S/D was formed by driving dopant from implanted second layer polysilicon. Portions of polysilicon under the nitride layer corresponding to the lower capacitor electrode oxidizes at a slower rate than the exposed portions of the polysilicon. Such sequence of steps forms a self-aligned lower capacitor electrode for a dynamic random access memory integrated circuit.

Semiconductor having self-aligned polysilicon electrode layer

A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.

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Hsinchu, Taiwan

Nan-Hsiung Tsai