Samsung Electronics Co., Ltd.

Nak-Won Heo

Kyo-Min Sohn

Chang-Sik Yoo

Sang-Bo Lee

Sang-Joon Hwang

Sung-Min Seo

Yun-Young Lee

Jung-Hwan Choi

Kyung-Ho Kim

Kye-Hyun Kyung

Chang-Hyun Bae

A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Semiconductor memory devices including redundancy memory cells

According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register.

Semiconductor memory devices and systems including data output circuits to output stored data during first output mode and output programmed data pattern during second output mode

Semiconductor memory device with a data output circuit configured to output stored data during a first type of read operation and configured to output at least one data pattern during a second type of read operation and methods thereof

Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Data output circuit and method in DDR synchronous semiconductor device

The example semiconductor memory device may include a memory cell, a storage unit configured to store at least one data pattern, a data output circuit configured to output the stored data during a first type of read operation and configured to output the at least one data pattern during a second type of read operation and an output control circuit for controlling the data output circuit such that the memory cell is not accessed during read operations of the second type. A first example method may include storing at least one data pattern in a storage unit, outputting the stored data within the memory cell in response to a first type of read operation and outputting the at least one data pattern in the storage unit in response to a second type of read operation and blocking access to the memory cell during read operations of the second type.

In a semiconductor memory device the power level of which is strengthened by using data input/output pads in a no connection state, and a method of strengthening the power of the semiconductor memory device at a stabilized power level, the semiconductor memory device comprises: a plurality of data input/output drivers; and a plurality of data input/output pads, each connected to a corresponding one of the plurality of data input/output drivers. A first subset of the data input/output pads are connected to respective data input/output pins of a package, and several or all of a remaining subset of the data input/output pads that are not connected to data input/output pins of the package are connected to power pins of the package.

Semiconductor memory device with strengthened power and method of strengthening power of the same

A semiconductor memory device that includes a memory cell connected to a wordline and a wordline voltage generator. The wordline voltage generator supplies a first negative voltage to the wordline in a standby state and supplies a second negative voltage that is lower with respect to ground than the first negative voltage to the wordline in a refresh operation. Accordingly, a leakage current generated at a transistor of a memory cell by gate-induced drain leakage (GIDL) is suppressed to enhance the performance of a refresh operation.

Semiconductor memory device and method of supplying wordline voltage thereof

Provided is a circuit for generating a data strobe signal used in a double data rate (DDR) synchronous semiconductor device. The circuit comprises a first logic unit capable of generating a pull up control signal responsive to first and second clock signals. A second logic unit is capable of generating a pull down signal responsive to the first and second clock signals. A data strobe buffer is capable of generating a data strobe signal responsive to the pull up and pull down control signals, the data strobe signal including a preamble. The first logic unit is capable of generating the preamble responsive to a first pulse of the first clock signal. And the data strobe signal is in a high impedance state responsive to a last pulse of the first clock signal.

Circuit for generating a data strobe signal used in a double data rate synchronous semiconductor device

An information processing system for controlling clock skew preferably includes a first and a second memory module, each of which has at last one semiconductor integrated circuit and is controlled by a chipset which can selectively control the time delay of an individual clock signal based on a stored value. The system further includes a clock line, which includes a first and a second clock line segment forming a closed loop and at least one data line connected between the chipset and a first termination device. By designing each of the first and the second clock line segments to be the same length as the data line, the propagation time of a clock signal and a data signal may be accurately matched.

Growing community of inventors

Suwon-si, South Korea

Nak-Won Heo