Samsung Electronics Co., Ltd.

Nak-jin Son

Ji-Young Kim

Yoo-Sang Hwang

Dae-Ik Kim

Jun Hyuk Seo

Dong-Il Bae

Gyo-young Jin

Yong-chul Oh

Du-Heon Song

Hyeoung-Won Seo

Se-myeong Jang

Wook-Je Kim

Kyung-Soo Kim

Dong-won Kim

Je-min Park

Keun-Ho Lee

Hyoung-sub Kim

Ho-in Ryu

Ui-hui Kwon

Young-Kwan Park

Wook-hyun Kwon

Chang-wook Jeong

Seon-Ah Nam

Yeon-Ho Park

Seung-Hyun Song

Gi-bong Lee

Kwang-Seok Lee

An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.

Integrated circuit device and method of manufacturing the same

A method of manufacturing a semiconductor device includes forming a plurality of active fins over a semiconductor substrate, sequentially forming first and second hard mask layers over the active fins, forming a first hard mask pattern by etching the second hard mask layer, trimming the first hard mask pattern to form a trimmed hard mask pattern, forming a first photo resist pattern over the first hard mask layer, forming second hard mask patterns by etching the first hard mask layer by using the trimmed hard mask pattern and the first photo resist pattern as an etching mask, and forming active fin patterns by etching the active fins by using the second hard mask patterns as an etching mask.

Method of manufacturing semiconductor device

Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at least an insulating layer, and a conductive plug structure electrically connecting the conductive line to the target connection region, wherein the conductive plug includes a first conductive plug having a first side wall, a bottom surface contacting the target connection region of the substrate, and a second side wall facing the first side wall of the conductive line, and a second conductive plug between the conductive line and the first conductive plug. The second conductive plug contacts both the first side wall of the conductive line and the second side wall of the first conductive plug.

Semiconductor devices including conductive plug

Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region in each of the third and fourth fins by doping impurities into the first to fourth fins on both sides of the first to fourth dummy gate structures by performing an ion implantation process simultaneously in the first and second regions; and removing the first doped region of the first fin and the second doped region of the third fin, or removing the first doped region of the second fin and the second doped region of the fourth fin.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.

Methods for fabricating a semiconductor device

A semiconductor device includes a substrate, a conductive pattern (e.g., a contact plug) on an active region of the substrate and having respective first and second sidewalls on opposite first and second sides of the conductive pattern, and first and second conductive lines (e.g., bit lines) on the substrate on respective ones of the first and second sides of conductive pattern and separated from the respective first and second sidewalls by asymmetric first and second air spaces.

Semiconductor devices using air spaces to separate conductive structures and methods of manufacturing the same

Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.

Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

Method of doping polysilicon layer that utilizes gate insulation layer to prevent diffusion of ion implanted impurities into underlying semiconductor substrate

According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.

Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same

A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gate insulating layer is formed on the first semiconductor layer and the substrate. Two gate electrodes are formed on the gate insulating layer such that the trench is located in between two gate electrodes. First and second impurity regions are formed in the substrate on both sides of each of the gate electrodes. Since the doped layer is locally formed in the trench area, the source and drain regions are completely separated from the heavily doped layer to weaken the electric field of PN junction, thereby improving refresh and preventing punchthrough between the source and drain.

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Gyeonggi-do, South Korea

Nak-jin Son