United Microelectronics Corp.

United Silicon Incorporated

Nai-Chen Peng

Tzyh-Cheang Lee

Ming-Tzong Yang

Ching-Hung Cheng

Chien-Hung Chen

Tri-Rung Yew

Coming Chen

Tzu-Ping Chen

Sung-Bin Lin

Shui-Chin Huang

Tsong-Minn Hsieh

Kuang-Pi Lee

Chung-Chin Shih

Chungchin Shih

Ming-Yin Hao

Chuan Fu Wang

Jih-Cheng Yeh

A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned above the data storage elements,

NAND-type non-volatile memory

The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first Pdoped drain region and a first Pdoped source region. The second PMOS transistor includes a gate and a second Pdoped source region. The first Pdoped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a Ndoped region. The floating gate overlaps with the N-well and extends to the Ndoped region. The overlapped region of the P-well and the Ndoped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

Single-poly EEPROM

A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

Memory device

A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Capacitor in an interconnect system and method of manufacturing thereof

An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor substrate. The spaced apart S/D regions define a channel region in between. A first dielectric layer such as silicon dioxide is disposed on the S/D regions. An assistant gate is stacked on the first dielectric layer. The assistant gate has a top surface and sidewalls. A second dielectric layer comprising a charge-trapping layer is uniformly disposed on the top surface and sidewalls of the assistant gate and is also disposed on the channel region. The second dielectric layer provides a recessed trough between the S/D regions. A conductive gate material fills the recessed trough for controlling said channel region.

Non-volatile memory with induced bit lines

A method is used to fabricate an electrically erasable programmable read only memory. First, a substrate is provided. Then, a doped polysilicon pillar is formed on the substrate. Furthermore, a source is formed in the substrate beneath the doped polysilicon pillar. Finally, the other structures of the memory are completed in sequence.

Fabrication method for an electrically erasable programmable read only memory

A fabrication method for an electrically erasable programmable read only memory is described in which the memory cell has a sharp-cornered polysilicon pillar in junction with the source region to enhance the source side Fowler-Nordheim tunneling effect. The fabrication method sequentially forms an oxide layer and a silicon nitride on a silicon substrate, and then patterns the oxide layer and the silicon nitride layer to form a plurality of trenches. A first doped polysilicon layer is then formed on the substrate and fills the trenches. A wet oxidation is then conducted to grow an oxide layer on the first doped polysilicon layer, from which a sharp-cornered doped polysilicon layer results. A first dielectric layer is further formed on the substrate and the doped polysilicon layer, followed by forming a floating gate on the first dielectric layer. After this, a second dielectric layer is formed on the substrate, covering the floating gate, and a control gate is formed on the second dielectric layer.

Electrically erasable and programmable read only memory device and manufacturing therefor

A process is disclosed for fabricating buried diffusion junction that can be combined with the shallow-trench isolation for the memory device cell unit transistor wherein both the junction and the isolation can be formed in the same layout. The buried diffusion is free from being inadvertently cut apart to cause open-circuiting. A bird's beak oxide layer is formed protecting the buried diffusion junction region from undesirable etching, thereby preventing from damaging consumption by etching. The buried diffusion junctions formed may serve as the source/drain region for the transistor.

Process of fabricating buried diffusion junction

A method of manufacturing a dual cylinder-shaped capacitor. The method includes the steps of forming a cylindrical oxide layer above a conductive layer, and then forming silicon nitride spacers and first oxide spacers on the sidewalls of the cylindrical oxide layer. Next, using the silicon nitride spacers, the first oxide spacers and the cylindrical oxide layer as a hard mask, the conductive layer is etched to form a separate lower electrode. Thereafter, the oxide layer is removed so that only the silicon nitride spacers remain. Subsequently, second oxide spacers and third oxide spacers are formed on the sidewalls of the silicon nitride spacers. Finally, the silicon nitride spacers are removed, and then the conductive layer is again etched to form the dual cylinder-shaped lower electrode.

Method of manufacturing a dual cylinder-shaped capacitor

A method is provided for use in a semiconductor fabrication process to form buried diffusion junctions in conjunction with shallow-trench isolation (STI) structures in a semiconductor device. This method features beak-like oxide layers formed to serve as a mask prior to the forming of the STI structures, which can prevent the subsequently formed buried diffusion junctions from being broken up during the process for forming the STI structures. Moreover, sidewall-spacer structures are formed on the sidewalls of a silicon nitride layer used as a mask in the ion-implantation process. This can prevent short-circuits between the buried diffusion junctions when the doped areas are annealed to be transformed into the desired buried diffusion junctions.

Growing community of inventors

Hsin-Chu, Taiwan

Nai-Chen Peng