International Business Machines Corporation

Globalfoundries Inc.

Nagashyamala R Dhanwada

Arun Joseph

William W Dungan

David James Hathaway

James Douglas Warnock

Leon Jacob Sigal

Ricardo H Nigaglioni

Gaurav Mittal

Spandana V Rachamalla

Arya Madhusoodanan

Anand Haridass

Charles Robert Lefurgy

Diwesh Pandey

Natesan Venkateswaran

Victor V Zyuban

Robert J Devins

Sungjae Lee

Michael R Scheuermann

Arjen Alexander Mets

Glenn E Holmes

Joseph Arun

David Kadzov

Youngsoo Shin

Jingcao Hu

Joseph K Morrell

Jose Luis P Correia Neves

Richard A Wachnick

Generating a contributor-based power abstract for a device, including: identifying a clock power component for each of a plurality of clock gating domains, identifying a switching characteristic for each of the clock gating domains, combining the switching characteristics for all of the clock gating domains into a domain combination list, performing a per-case simulation based at least on the domain combination list, calculating an effective capacitance for each of the clock gating domains based at least on the per-case simulation, and generating a power abstract for each of the clock gating domains based at least on the effective capacitance.

Methods for generating a contributor-based power abstract for a device

A method and system for improving the performance of a computer in identifying and mitigating electromigration violations of a semiconductor device. A set of library gates is obtained and parasitic layout extraction is performed for each gate in the set of library gates to generate an extracted netlist. One or more passes of an electromigration analysis of the extracted netlist are performed to characterize each gate over a set of input parameters and to generate a maximum slew rate (MAX_SLEW) table and a maximum capacitance (MAX_CAP) table.

Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips

Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.

Method for efficient localized self-heating analysis using location based DeltaT analysis

Method for efficient localized self-heating analysis using location based deltat analysis

A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner&#x2014;based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.

Early analysis and mitigation of self-heating in design flows

A method for generating a power model for a device includes identifying a device-level set of power contributors for a given state of the device, wherein each power contributor in the device-level set of power contributors contributes to power dissipation when the device is in the given state, and generating the power model for the device based on the device-level set of power contributors, wherein the power model is independent of process, voltage, and temperature.

Contributor-based power modeling of microprocessor components

A system, method and computer program product for enabling efficient and accurate post-silicon leakage power characterization of semiconductor chips at very high temperatures. The system and method can be used to estimate dynamic power usage at a sub-component level. The system and method determines leakage power during test time while running a workload in a manner such that a wider range of temperatures can be characterized on a tester that does not have precise temperature control, i.e., does not require or use external heaters. Additional power management functionality for a semiconductor device is provided while running a workload that breaks down total power measured into workload dependent and workload-independent subcomponents.

Method for breaking down hardware power into sub-components

A method of generating system level power information for an embedded application configured to execute on a multi-core system-on-chip (SoC), which includes configuring a simulation model of hardware of the SoC that executes the embedded application; loading one or more software components of the embedded application into the simulation model of the SoC hardware; executing the one or more software components of the embedded application on the simulation model, and extracting state information about both the software components of the embedded application and hardware components of the SoC; determining, from the hardware state information, per-cycle energy values for the hardware components of the SoC; and creating a power profile from the software state information by accumulating the per-cycle energy values and assigning the per-cycle energy values to corresponding software components.

System level power profiling of embedded applications executing on virtual multicore system-on-chip platforms

A development system for developing new peripheral software code for new peripheral hardware that will be used in a new integrated system. The development system includes a legacy, or preexisting, integrated system substantially the same as the new integrated system. A model of the new peripheral hardware is made. Each I/O register of the model is mapped into memory-mapped I/O space. Development code corresponding to the new peripheral software code is executed on the preexisting hardware so as to interact with the model via the memory-mapped I/O space. In one embodiment, the model is executed as an embedded model on the preexisting integrated system. In another embodiment, the model is executed as a non-embedded model on a hardware descriptive language simulator.

System and method for developing embedded software in-situ

Voltage islands enable a core-level power optimization of ASIC/SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage island partitions and the voltage level assignment are performed simultaneously in a floorplanning context due to the physical constraints involved. This leads to a floorplanning formulation that differs from the conventional floorplanning for ASIC designs. Such a formulation of a physically aware voltage island partitioning and method for performing simultaneous voltage island partitioning, level assignment and floorplanning are described, as are the definition and the solution of floorplanning for voltage island based designs executed under area, power, timing and physical constraints. The physical planning of voltage islands includes: a) characterizing cell clusters in terms of voltages and power consumption values; b) providing a set of cell clusters that belong to a single voltage island Random Logic Macro (RLM); and c) assigning voltages for the voltage island RLMs, all within the context of generating a physically realizable floorplan for the design.

Method of physical planning voltage islands for ASICs and system-on-chip designs

An abstraction based multi-phase method for VLSI chip floorplanning is described. The abstraction based approach provides a solution to macro floorplanning in the presence of leaf level intermediate logic, and achieves it without loss of accuracy in the results. Annotations generated during abstraction are presented as floorplanning constraints which account for the abstracted data. The floorplanning and placement algorithms handle detailed netlists consisting of large blocks and small leaf level cells in an efficient manner. The abstraction based approach phases out by abstracting the leaf level logic (thus reducing the solution space of the floorplanner) and reintroducing them in the form of floorplan constraints (to account for the presence of the leaf level logic while determining the location of large blocks). The abstraction and bundling phases achieves a significant improvement in the performance of a simulated annealing based floorplanner. The overall concept of driving a floorplanning algorithm with a path based hyper-edge representation also helps to provide structural information about the netlist to the floorplanner.

Method for optimizing a VLSI floor planner using a path based hyper-edge representation

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Fishkill, NY, United States of America

Nagashyamala R Dhanwada