Samsung Electronics Co., Ltd.

Naein Lee

Jongmin Baek

Sanghoon Ahn

Wookyung You

Sangho Rha

Byunghee Kim

Dongsuk Shin

Vietha Nguyen

Dong Hyuk Kim

Hoi Sung Chung

Taejin Yim

Jiwon Kang

Ho-jin Lee

Kwangjin Moon

Pankwi Park

Donghyun Roh

Byung-Kwon Cho

Hak-Sun Lee

Thomas Oszinda

YoungWoo Cho

Songyi Han

Jiwon Yun

Young-ju Park

Chulwoong Lee

Inoue Naoya

Jiyoung Kim

Ju-Il Choi

Pil-Kyu Kang

Woojin Lee

Kyu-Hee Han

Hyun Uk Park

Jin Ho An

Jung Nyoung Heo

Seokho Kim

Sang Hoon Ahn

Kyuhee Han

Hyunbae Lee

Sukchul Bang

Soonmoon Jung

JuBin Seo

Deokyoung Jung

Sujeong Park

Doo-Sung Yun

Sangshin Jang

Hyeoksang Oh

Seungyong Yoo

Hyoju Kim

Keeyoung Jun

Hoyun Jeon

Woochoel Noh

Wonkyu Han

Gyeongyun Han

Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

Semiconductor devices and methods of fabricating the same

A method of fabricating a semiconductor device, the method including forming a deposition active layer and a guide pattern on a semiconductor substrate such that the guide pattern delimits an exposed surface of the deposition active layer; and selectively depositing a metal-containing layer on the exposed surface of the deposition active layer exposed by the guide pattern, wherein the deposition active layer is a nonmetal layer.

Method of fabricating a semiconductor device

A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.

Semiconductor device and method of fabricating the same

A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer.

Method of manufacturing semiconductor device using a plurality of etch stop layers

A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.

Planarized interlayer dielectric with air gap isolation

A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

Semiconductor devices having staggered air gaps

A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.

A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

A semiconductor device may include a substrate, a first interlayered insulating layer on the substrate having openings, conductive patterns provided in the openings, first to fourth insulating patterns stacked on the substrate provided with the conductive patterns, and a second interlayered insulating layer provided on the fourth insulating pattern.

Semiconductor devices

A method of fabricating a semiconductor device including an interlayer insulating layer and interconnections is provided. An interlayer insulating layer is formed on a substrate. An opening is formed in the interlayer insulating layer. A degassing process is performed by irradiating the interlayer insulating layer having the opening with microwaves. A K-value recovery process is performed by irradiating the interlayer insulating layer having the opening with UV light. A conductive layer is formed in the opening. The degassing process and the K-value recovery process are performed as an in-situ process.

Method of forming semiconductor device having dielectric layer and related system

The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Semiconductor devices including gaps between conductive patterns

A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.

Method of treating a porous dielectric layer and a method of fabricating a semiconductor device using the same

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Seoul, South Korea

Naein Lee