Lg Semicon Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Nae Hak Park

Chang Jae Lee

Yong Kwon Kim

Chang Soo Kim

Yun Hee Kim

The method of forming a plug of a semiconductor device includes sequentially forming a conductive film and an insulation film over a semiconductor substrate having a high density region and a low density region. The high density region has a greater number of structures formed thereover than the low density region. Next, a first CMP (chemical mechanical polishing) process, in which slurry for removing insulating film is used, is performed to selectively remove the insulating film and expose a top surface of the conductive film. Then a second CMP process, in which slurry for removing conductive film is used, is performed to selectively remove the conductive film and the insulating film and expose structures in the high density region.

Method for forming plug of semiconductor device

A method for forming metal line of a semiconductor device in which, if the aspect ratio of the contact holes is big, contact holes are buried with a CVD method using the HDP method, and the line process is simplified to improve the reliability is disclosed, including the steps of forming an insulating film having a contact hole on a semiconductor substrate; forming a barrier metal layer on the insulating film including the contact hole; and forming a metal line layer on the barrier metal layer with a CVD method using a high density plasma.

Method for forming metal line of semiconductor device

A method of forming an interconnection for a semiconductor device includes the steps of: forming a lower conductive line on a semiconductor substrate and forming a first insulating layer on the semiconductor substrate and the lower conductive line; patterning the first insulating layer to form a first insulating layer pattern which is narrower than the lower conductive line on the lower conductive line; forming a second insulating layer on an overall surface of the substrate and on the first insulating layer pattern, to planarize a surface of the second insulating layer; patterning the second insulating layer to expose a surface of the first insulating layer pattern and to form a first trench wider than the first insulating layer pattern on an upper portion of the first insulating pattern; removing the first insulating layer pattern, to thereby form a second trench at a lower portion of the first trench; and filling the first and second trenches with conductive material, to thereby form an upper conductive line.

Method for forming interconnection of semiconductor device

A method for forming an interconnection pattern in a semiconductor device for reducing metallic reflection, includes the steps of forming a conductive layer on a substrate, polishing the conductive layer to form a rugged surface on the conductive layer, and selectively removing the polished conductive layer to form the interconnection pattern.

Method for forming interconnection in semiconductor pattern device

A method for forming a Damascene structured multi-layered metal wiring for a semiconductor element, which includes the steps for forming a first insulating layer on the surface of a semiconductor substrate, forming a lower metal wiring pattern on the first insulating layer, forming a second insulating layer on the first insulating layer and the lower metal wiring pattern, forming contacts by subjecting the second insulating layer to etching, successively depositing first and second upper metals over the second insulating layer and the contact, subjecting the second upper metal to etching until the first upper metal is exposed, and forming an upper metal wiring pattern having a double metal structure by subjecting the first upper metal to etching until the second insulating layer is exposed. The upper wiring layer is preferably formed of aluminum deposited by a sputtering method and tungsten deposited by a chemical vapor deposition method.

Growing community of inventors

Seoul, South Korea

Nae Hak Park