Southeast University

Na Bai

Longxing Shi

Jun Yang

Xinning Liu

Yuan Chen

Jie Li

Hong Chang

Chen Hu

Jiafeng Zhu

Yue Feng

Cai Gong

Fei Pan

Yifeng Deng

Yingcheng Xia

Peng Cao

Weiwei Shan

Chao Wang

Xuexiang Wang

Tao Zhao

Ming Ling

Aiguo Bu

A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.

Circuit for enhancing robustness of sub-threshold SRAM memory cell

Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal.

Noise current compensation circuit

The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.

Power-on-reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage

A high-density and high-robustness sub-threshold memory cell circuit, having two PMOS transistors Pand Pand five NMOS transistors N&#x2dc;N, wherein, the each base electrode of the two PMOS transistors and NMOS transistors N, N, and Nis connected with the local grid electrode respectively; the base electrode of the NMOS transistors Nand N, are grounded respectively; the NMOS transistor Nform an phase inverter with the PMOS transistor P, and the NMOS transistor Nform another phase inverter with the PMOS transistor P; the two phase inverters are connected with each other in a cross coupling manner via the cut-off NMOS transistor N, the output end of the phase inverter Nand Pdirectly connected to the input end of the phase inverter Nand P, and the output end of the phase inverter Nand Pconnected to the input end of the phase inverter Nand Pvia the cut-off NMOS transistor N; the NMOS transistor Nis connected with the write bit line (WBL) of the phase inverter Nand P, and the NMOS transistor Nis connected with the NOT WBL and read word line (RWL) of the phase inverter Nand P

Sub-threshold memory cell circuit with high density and high robustness

A capacity and density enhancement circuit for a sub-threshold memory unit array which can decrease the drain current in the bit lines and enhance the pull-up capability of memory cells. The capacity and density enhancement circuit is composed of a first enhancement transistor, a second enhancement transistor, a first mask transmission gate, a second mask transmission gate, a first logic memory capacitor and a second logic memory capacitor.

Capacity and density enhancement circuit for sub-threshold memory unit array

Growing community of inventors

Jiangsu, China

Na Bai