Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Myung Sam Kang

Young Gwan Ko

Mi Sun Hwang

Tae Hong Min

Moon Il Kim

Jung Hyun Park

Chang Sup Ryu

Yong Koon Lee

Young Chan Ko

Jin Su Kim

Ki Seok Kim

Chang Bae Lee

Seon Hee Moon

Sa Yong Lee

Ye Jeong Kim

Yong Jong Park

Ji Eun Kim

Jeong Ho Lee

Ok Tae Kim

Bong Ju Cho

Seon Ha Kang

Kil Yong Yun

Kwang Hee Kwon

Myung Jun Park

Seung Eun Lee

Jae Joon Lee

Sang Kyu Lee

Jeong Woo Park

Jung Hyuk Jung

Jin Gu Kim

Young Kwan Lee

Woon Chul Choi

Seung Ryong Kook

Shang Hoon Seo

Hye Min Bang

Je Gwang Yoo

Yong Jin Seol

Nam Keun Oh

Seok Hwan Ahn

Jin Yong An

Shuhichi Okabe

Min Jae Seong

Il Jong Seo

Jun Ah

Sang Duck Kim

Jong Gyu Choi

Hoe Ku Jung

Young Ji Kim

Han Bit Kim

Ji Hong Jo

Tae Hoon Kim

Kyung Ho Lee

Sung Han Kim

Doo Hwan Lee

Jeong Min Cho

Jung Woo Choi

Sung Won Jeong

Hye Jeong Kim

Jin Gyun Kim

Seung Yeop Kook

Joo Hwan Jung

Min Jung Cho

Jung Han Lee

Suk Hyeon Cho

Jeong Seok Kim

Ki Ju Lee

Byoung Youl Min

Jeong Il Lee

Han Saem Lee

Jin Ho Hong

Jin Yong Ahn

Jin Hyuk Jang

Eung Suek Lee

Ki Jung Sung

Yong Jin Park

Hye Won Jung

Ju Hee Park

Jong Kuk Hong

Keung Jin Sohn

Soon Oh Jung

Dae Hui Jo

Chin Kwan Kim

Tae Eui Kim

Gil Yong Shin

Sang Yul Ha

Dong Keun Lee

A semiconductor package including a core structure, in which a first and second semiconductor chips and passive components are embedded, a connection structure disposed on a first side of the core structure, and including a redistribution layer electrically connected to the first and second semiconductor chips and the passive components, and a metal pattern layer and a backside wiring layer disposed on a second side of the core structure opposing the first side, and spaced apart from each other. The core structure includes a first metal layer surrounding the first semiconductor chip, a second metal layer surrounding the first semiconductor chip, and the first metal layer, a third metal layer surrounding the second semiconductor chip, and a fourth metal layer surrounding the second semiconductor chip, the passive components, and the third metal layer, and each of the first to fourth metal layers is electrically connected to the metal pattern layer.

Semiconductor package and antenna module comprising the same

A fan-out semiconductor package including a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer.

Fan-out semiconductor package

A method includes forming a first package structure including a first connection member including a first redistribution layer, a first frame having a first through-portion, a first semiconductor chip having a connection pad electrically connected to the first redistribution layer, and a first encapsulant covering a portion of each of the first frame and the first semiconductor chip, forming a second package structure including a second connection member including a second redistribution layer, a second semiconductor chip having a second connection pad, and a second encapsulant covering a portion of the second semiconductor chip, forming a first through-via, the first through-via electrically connecting to the second redistribution layer, and laminating the first package structure on the second package structure. After the laminating, the first through-via penetrates through the first frame, the first encapsulant, and a portion of the first connection member, and is electrically connected to the first redistribution layer.

Semiconductor package

A method including forming a frame having an opening, forming a first metal layer, forming a first encapsulant, forming an insulation layer on the first metal layer, forming a first through-hole and a second through-hole penetrating the insulation layer and the first encapsulant, forming a second metal layer and a third metal layer, forming a second encapsulant, forming a first metal via and a second metal via penetrating the second encapsulant and a metal pattern layer on the second encapsulant, and forming a connection structure. The first metal layer and the second metal layer respectively are formed to extend to a surface of each of the first encapsulant and the frame, facing the metal pattern layer, and the first metal layer and the second metal layer are connected to the metal pattern layer through the first metal via and the second metal via having heights different from each other.

A semiconductor package is provided. The semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a heat sink structure comprising a lower heat sink pattern disposed on the first semiconductor chip, a metal film pattern disposed on the lower heat sink pattern, and an insulating film disposed on side walls of the lower heat sink pattern and side walls of the metal film pattern, an interposer disposed on the heat sink structure, and a solder ball which connects the heat sink structure and the interposer.

A multilayer seed pattern inductor includes a magnetic body and an internal coil part. The magnetic body contains a magnetic material. The internal coil part is embedded in the magnetic body and includes connected coil conductors disposed on two opposing surfaces of an insulating substrate. Each of the coil conductors includes a seed pattern formed of at least two layers, a surface coating layer covering the seed pattern, and an upper plating layer formed on an upper surface of the surface coating layer.

Multilayer seed pattern inductor and manufacturing method thereof

A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.

A coil component includes: a body including a magnetic material, coil pattern layers disposed in the magnetic material, a core portion surrounded by the coil pattern layers, and an insulating layer disposed in the core portion and between adjacent coil pattern layers among the coil pattern layers, wherein each of the coil pattern layers comprises a spiral-shaped pattern; and an external electrode disposed on the body.

Coil component

A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.

Semiconductor package including frame in which semiconductor chip is embedded

A semiconductor package includes a first connection member including a first redistribution layer, a first frame disposed on the first connection member, a first semiconductor chip disposed on a first through-portion and having a connection pad, a first encapsulant covering a portion of each of the first frame and the first semiconductor chip and filling at least a portion of the first through-portion, a second connection member disposed on the first encapsulant and including a second redistribution layer, a second semiconductor chip disposed on the second connection member and having a second connection pad, a second encapsulant covering a portion of the second semiconductor chip, and a first through-via penetrating through the first frame, the first encapsulant, and a portion of the first connection member, and electrically connecting the first and second redistribution layers to each other.

A semiconductor package includes a connection structure including an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer, a frame disposed on the connection structure and having a through-hole, a semiconductor chip disposed in the through-hole on the connection structure and having a connection pad disposed to face the connection structure, and a passive component disposed on the frame.

A semiconductor package includes a core structure having a first through-hole and including a frame having an opening, a passive component disposed in the opening, a first encapsulant covering the frame and the passive component, a first metal layer disposed on an inner surface of the first through-hole, and a second metal layer disposed on an inner surface of the opening; a first semiconductor chip disposed in the first through-hole and having a first connection pad; a second encapsulant covering the core structure and the first semiconductor chip; a connection structure disposed on the core structure and the first semiconductor chip and including a redistribution layer; and a metal pattern layer disposed on the second encapsulant. The first and second metal layers are connected to the metal pattern layer through first and second metal vias having heights different from each other.

A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.

Semiconductor package and antenna module including the same

A coil electronic component includes a plurality of coil layers including coil patterns and connection patterns. The coil patterns are disposed between the connection patterns. The connection patterns are at least partially exposed from the coil electronic component. The coil electronic component further includes connection electrodes connecting the connection patterns formed in different coil layers of the plurality of coil layers with each other, and external electrodes connected to the connection electrodes and at least partially enclosing the connection electrodes.

Coil electronic component

There are provided an inductor and a method of manufacturing the same. The inductor includes: a body including a coil part; and cover parts disposed on upper and lower surfaces of the body. The coil part includes a plurality of through-vias penetrating through the upper and lower surfaces of the body and connection patterns disposed on the upper and lower surfaces of the body, disposed in the cover parts, and connecting the plurality of through-vias to each other.

Inductor and method of manufacturing the same

Growing community of inventors

Suwon-si, South Korea

Myung Sam Kang