Skhynix Inc.

Hyundai Electronics Industries Co. Ltd.

Hyundai Electronics Industries

Myoung Soo Kim

Cheol Kyu Bok

Keun Do Ban

Jae Chang Jung

Ki Ho Baik

Keun Kyu Kong

Hyeong Soo Kim

Jung Gun Heo

Hyoung Gi Kim

Geun Su Lee

Ki Lyoung Lee

Hyung Gi Kim

Jung Hyung Lee

Min Ho Jung

Chi Hyeong Roh

Jin Ki Jung

Hyun Kyung Shim

Jin Soo Kim

Cha Won Koh

Chang Moon Lim

Jun Taek Park

Jeong Su Park

In Hwan Lee

Jae Hak Choi

Byoung Hoon Lee

Hae Jung Lee

Sang Do Lee

Chang Il Oh

Sang Kil Kang

A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.

Nano-scale structures

A fine pattern structure includes a lower hard mask layer on a pattern formation layer having a first region and a second region, first upper hard mask patterns disposed on the lower hard mask layer in the first region to expose portions of the lower hard mask layer, a second upper hard mask pattern covering the lower hard mask layer in the second region, guide patterns on the first and second upper hard mask patterns, neutralization patterns on the exposed portions of the lower hard mask layer in the first region, a first block co-polymer layer covering the guide patterns in the first region and the neutralization patterns, and a second block co-polymer layer covering the guide pattern in the second region.

Fine pattern structures having block co-polymer materials

Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.

Method of manufacturing a semiconductor device having bit line structures disposed in trenches

A method of fabricating a pattern comprising sequentially forming a pattern formation layer and a neutral layer on over a substrate having in a first regions and a second regions, forming guide patterns on first portions of over the neutral layer in the second regions, forming a first block copolymer layers on over second portions of the neutral layer in the first regions, phase-separating the tint block copolymer layers such that each of the first block copolymer layers includes to form first polymer blocks having a first phase and first polymer blocks having a second phase, removing the guide patterns to form openings that expose the first portions of the neutral layer in the second region, forming a second block copolymer layer on over the phase-separated first block copolymer layers and in the openings, phase-separating the second block copolymer layer into to form second polymer blocks having the first phase and second polymer blocks having the second phase removing the second polymer blocks having the second phase and the first polymer blocks having the second phase, and etching the neutral layer and the pattern formation layer using the first polymer blocks having the first phase and the second polymer blocks having the first phase as an etch masks.

Methods of fabricating a pattern using the block co-polymer materials

Semiconductor devices having bit line structures disposed in trenches

Methods of forming fine patterns are provided. The method includes reinforcing a hydrophobic property of a hard mask layer using a surface treatment process to form a neutral layer, forming a block co-polymer layer on the neutral layer, and phase-separating the block co-polymer layer into first domains and second domains.

Methods of fabricating fine patterns

A fine pattern structure includes a layer having or including alternating protrusion portions and recess portions, polymer patterns disposed in recess regions formed by the recess portions, brush patterns disposed on top surfaces of the protrusion portions, and a block co-polymer layer including first polymer block patterns formed on the brush patterns and second polymer block patterns formed on the polymer patterns.

A semiconductor device includes a substrate and a plurality of active pillars disposed on the substrate and spaced apart from each other by trenches. Each of the active pillars includes a buried metal silicide pattern and an active region stacked on the buried metal silicide pattern, and the active region includes impurity junction regions.

Semiconductor devices having buried metal silicide layers and methods of fabricating the same

A method for fine pattern structures includes forming a pattern formation layer over a first region and a second region of a substrate, forming a first block co-polymer layer in the first region, forming a second block co-polymer layer in the second region, etching the first and second block co-polymer layers, and forming the fine pattern structure in the pattern formation layer in the first region without forming a pattern in the pattern formation layer in the second region.

Fine pattern structures having block co-polymer materials and methods of fabricating the same

Various embodiments are directed to fine pattern structures, such as fine pattern structures having block co-polymer materials, methods of forming fine pattern structures with block co-polymer materials, and methods of fabricating semiconductor devices including fine pattern structures with block co-polymer materials. According to some embodiments, a method of fabricating a fine pattern structure includes providing a layer of alternating protrusion portions and recess portions, forming polymer patterns in recess regions formed in the recess portions, forming brush patterns on top surfaces of the protrusion portions, forming first polymer block patterns on the brush patterns and second polymer block patterns on the polymer patterns, and removing the second polymer block patterns and the polymer patterns.

Methods of fabricating nano-scale structures are provided. A method includes forming a first hard mask pattern corresponding to first openings in a dense region, forming first guide elements on the first hard mask pattern aligned with the first openings, and forming second hard mask patterns in a sparse region to provide isolated patterns. A blocking layer is formed in the sparse region to cover the second hard mask patterns. A first domain and second domains are formed in the dense region using a phase separation of a block co-polymer layer. Related nano-scale structures are also provided.

Methods of fabricating nano-scale structures and nano-scale structures fabricated thereby

The method includes forming an array of first separation walls on an underlying layer. A block co-polymer (BCP) layer is formed to fill inside regions of the first separation walls and gaps between the first separation walls. The BCP layer is phase-separated to include first domains that provide second separation walls covering inner sidewalls and outer sidewalls of the first separation walls and second domains that are separated from each other by the first domains.

Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby

A semiconductor device includes a cell mask pattern disposed in a cell region of a mask substrate and a vernier mask pattern disposed in a vernier region of the mask substrate. The vernier mask pattern includes a variable mask pattern portion to transfer a different shape of pattern depending on the magnitude of exposure energy.

Growing community of inventors

Seongnam, South Korea

Myoung Soo Kim