Samsung Electronics Co., Ltd.

Myeong-Cheol Kim

Jin-wook Lee

Cheol Kyu Kim

Young-Ju Park

Do-hyoung Kim

Tae-hyuk Ahn

Dong-Chan Kim

Kyung-Yub Jeon

Min-Chul Sun

Kyoung-Sub Shin

Doo-youl Lee

Sang-min Lee

Si-Young Choi

Bum-Soo Kim

Byeong-Yun Nam

Shi-Yong Yi

Hak-Sun Lee

Hee-Don Jeong

Jae-Ho Min

Bo-un Yoon

Jaehun Seo

Yong-jin Kim

Sang-Bom Kang

Kyeong-Koo Chi

Chang-Jin Kang

Hong-bae Park

Jeong-yun Lee

Ho-young Kim

Siyoung Choi

Ja-hum Ku

In-Ho Kim

Byoung-ho Kwon

Yong-Joon Choi

Geum-jung Seong

Jae-Kwang Choi

Sung-kee Han

Myung-Hoon Jung

Jae-ho Min

Hyung-yong Kim

Soo-Yeon Jeong

O-Ik Kwon

Ji-Eun Han

Dong-kwon Kim

Kisoo Chang

Seung-Jae Lee

Dong-Hyun Kim

Jae-Hwang Sim

Sang-Su Kim

Sung-Ho Kim

Jun Hyuk Seo

Ki-Il Kim

Sang-sup Jeong

Ji-Hoon Cha

Ji-young Lee

Sung-Woo Lee

Yong-Ho Jeon

Kwan-heum Lee

In-Wook Cho

Jung-hyeon Lee

Keun-Hee Bai

Chang-jin Kang

Jong-Seo Hong

Gyung-Jin Min

Bok-Young Lee

Do-Haing Lee

Seung-mo Ha

Seung-Young Son

Jong-Chan Shin

Dong-hoon Khang

Man-Hyoung Ryoo

Jin-hee Kim

Yoo-Jung Lee

Hak-sun Lee

Heung-sik Park

Jung-Chan Lee

Choong-Ho Lee

Ji-Young Kim

Jong-Wook Lee

Sang-Jin Kim

Hee-Soo Kang

Hyun-Jo Kim

Sang-hyun Lee

Ki Il Kim

Cha-Won Koh

Yong-Hoon Kim

Jae-yup Chung

Kwang-sub Yoon

Seong-woon Choi

Soo-Hun Hong

Ju-Bum Lee

Doo-Young Lee

Wook-Je Kim

Hyung-joon Kwon

Yong-Kug Bae

Seok-hwan Oh

Hong-Gun Kim

Eun-Kee Hong

Hyoung-Sub Kim

Ju-Seon Goo

Woo-cheol Lee

In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

Methods of manufacturing semiconductor devices by etching active fins using etching masks and forming source/drain layers on the active fins

Methods of manufacturing semiconductor devices by etching active fins using etching masks

Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

Field effect transistor having fin base and at least one fin protruding from fin base

A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

Integrated circuit device and method of manufacturing the same

A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Method of manufacturing semiconductor device having stressor

Semiconductor device having stressor and method of manufacturing the same

Methods of manufacturing finFET semiconductor devices

Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.

Methods of fabricating FinFET semiconductor devices including dummy structures

Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

Semiconductor device and method for fabricating the same

A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.

Method of forming a pattern

Growing community of inventors

Suwon-si, South Korea

Myeong-Cheol Kim