International Business Machines Corporation

Infineon Technologies Ag

Other

Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Munir D Naeem

Byeong Yeol Kim

David M Dobuzinsky

Kangguo Cheng

Lawrence Alfred Clevenger

Gangadhara Swami Mathad

Rajiv M Ranade

Effendi Leobandung

Johnathan E Faltermeier

Masaki Narita

Brian L Tessier

Virinder Grewal

James Patrick Norum

Stuart M Burns

Bruno Spuler

Ramachandra Divakaruni

Richard Stephan Wise

Rolf Weis

Rama Divakaruni

Larry Alan Nesbit

Hiroyuki Akatsu

Heon Lee

Nancy Anne Greco

Thomas Safron Kanarsky

Gregory Costrini

Chienfan Yu

Christopher D Sheraw

Jeremy K Stephens

Matthew J Sendelbach

Gerhard Kunkel

Shahid Ahmad Butt

Xiaomeng Chen

Ernest N Levine

Larry Clevenger

Satish D Athavale

Young-Jin Park

Brian S Lee

Michael Maldei

Chi-Hua Yang

Armin M Reith

Rosemary Christie

Frank D Tamweber, Jr

Elizabeth Morales

Stephan P Kudelka

Steve Greco

Walter W Kocon

David Mark Dobuzinksy

Lawrence A Clavenger

Ting-Hao Wang

A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.

Embedded DRAM memory cell with additional patterning layer for improved strap formation

An integrated circuit including a trench capacitor has a semiconductor region in which a material composition varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material, such as germanium, in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. The trench capacitor has an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory ('DRAM') cell, for example.

Enhanced capacitance trench capacitor

The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.

A method of fabricating a trench capacitor is provided in which a material composition of a semiconductor region of a substrate varies in a quantity of at least one component therein such that the quantity alternates with depth a plurality of times between at least two different values. For example, a concentration of a dopant or a weight percentage of a second semiconductor material in a semiconductor alloy can alternate between with depth a plurality of times between higher and lower values. In such method, the semiconductor region can be etched in a manner dependent upon the material composition to form a trench having an interior surface which undulates in a direction of depth from the major surface of the semiconductor region. Such method can further include forming a trench capacitor having an undulating capacitor dielectric layer, wherein the undulations of the capacitor dielectric layer are at least partly determined by the undulating interior surface of the trench. Such trench capacitor can provide enhanced capacitance, and can be incorporated in a memory cell such as a dynamic random access memory ('DRAM') cell, for example.

Method of forming enhanced capacitance trench capacitor

A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.

Shallow trench isolation structure compatible with SOI embedded DRAM

Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices

Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.

Poly filled substrate contact on SOI structure

This invention provides a hybrid orientation (HOT) semiconductor-on-insulator (SOI) structure having an isolation region, e.g. a shallow trench isolation region (STI), and a method for forming the STI structure that is easy to control. The method of forming the isolation region includes an etch of the insulating material, selective to the semiconductor material, followed by an etch of the semiconductor material, selective to the insulating material, and then filling any high aspect ratio gaps with a CVD oxide, and filling the remainder of the STI with an HDP oxide.

Subground rule STI fill for hot structure

A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.

STI formation for vertical and planar transistors

A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.

Reduced cap layer erosion for borderless contacts

A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.

Method for dry etching deep trenches in a substrate

A method of forming extruded structures from a polycrystalline material and structures formed thereby. The method generally entails forming a structure that comprises a polycrystalline material constrained by a second material in all but one direction, with the polycrystalline material having a patterned surface that is normal to the one direction. The polycrystalline material is then selectively heated, during which the second material restricts thermal expansion of the polycrystalline material in all but the one direction normal to the surface of the polycrystalline material. As a result, stresses are induced in the polycrystalline material that cause grain growth from the surface of the polycrystalline material in the one direction. The growth of an individual grain produces an extruded structure that projects above the surface of the polycrystalline material. When appropriately configured, nano-scale structures formed in accordance with this invention can be an operative component of a wide variety of devices, including digital recording media.

Polycrystalline material with surface features projecting from a surface thereof

A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) is formed over a semiconductor region (e.g., a silicon substrate). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening

A method of preventing or at least reducing the likelihood of bridging between adjacent micro-scale polycrystalline structures, and particularly to reducing electrical shorting between adjacent metallization lines of a microcircuit. The method generally entails forming a multilayer structure that comprises a polycrystalline layer and at least one constraining layer, and then patterning the multilayer structure to yield a first line and a second line that is narrower in width than the first line. The first line has a patterned edge that is spaced apart from a patterned edge of the second line, so that the first and second lines are electrically insulated from each other. One or more features associated with the first line are then formed that prevent bridging between the first and second lines if excessive lateral grain growth subsequently occurs along the patterned edge of the first line. Suitable features include patterning the multilayer structure to form a dummy line between and spaced apart from the first and second lines, patterning holes near the patterned edge of the first line, forming the patterned edge of the first line to have teeth that project toward the second line and are closer to the second line than the remainder of the patterned edge between the teeth, and forming the patterned edge of the first line to be stepped so that the first line has corner regions at opposite ends of the patterned edge that are closer to the second line than the remainder of the patterned edge between the corner regions. The invention also encompasses multilayer structures formed in accordance with the method.

Method of preventing bridging between polycrystalline micro-scale features

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Poughkeepsie, NY, United States of America

Munir D Naeem