Mitsubishi Electric Corporation

Munetaka Noguchi

Toshiaki Iwamatsu

A silicon carbide semiconductor device includes a drift layer of n-type formed on a semiconductor substrate composed of silicon carbide, a well region of p-type formed on a surface portion of the drift layer, a source region of p-type formed on a surface portion of the well region, a gate insulating film formed in contact with the source region, the well region, and the drift layer, and a gate electrode formed on the gate insulating film. In the silicon carbide semiconductor device, oxygen is contained in a region having a predetermined thickness from an interface between the well region and the gate insulating film toward the well regions side.

Silicon carbide semiconductor device, power conversion device, and manufacturing method of silicon carbide semiconductor device

In a SiC-MOSFET, to increase the threshold voltage while reducing the channel resistance is difficult. And, when the channel resistance is lowered, the reliability may be reduced in such a manner that a current may flow when the device is turned off and malfunction may occur when the device is used as a normally-off device. According to the present invention, the threshold voltage is increased while the channel resistance is reduced, and reliability when used as a normally-off device is improved by adding at least any of sulfur, selenium, and tellurium to the channel region of the SiC MOSFET.

Silicon carbide semiconductor device

Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof, a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole, and a second main electrode provided on a second main surface of the semiconductor substrate.

Growing community of inventors

Tokyo, Japan

Munetaka Noguchi