Samsung Electronics Co., Ltd.

Lg Semicon Co., Ltd.

Mun-Mo Jeong

Chang-Huhn Lee

Makoto Yoshida

Wook-je Kim

Jun-Hee Lim

Sang-Gi Ko

Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

Semiconductor device with gate spacer of positive slope and fabrication method thereof

A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than a width of the bitline.

Bitline of semiconductor device having stud type capping layer and method for fabricating the same

A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.

Semiconductor device and method for fabricating the same using damascene process

A semiconductor device having a contact hole capable of maintaining contact resistance of a contact connecting multi-layered interconnections with each other and a method for manufacturing the same are provided. An interconnection layer, a capping layer, and an etching stopper are sequentially formed on a semiconductor substrate. An interlayer insulating layer is deposited over the resulting structure. The etching stopper is formed of a material having a high etching selectivity with respect to the interlayer insulating layer. Then a first contact hole is formed to expose the surface of the etching stopper by etching a predetermined portion of the interlayer insulating layer. Either the etching stopper exposed by the first contact hole or the etching stopper exposed by the first contact hole and part of the capping layer are etched to form a second contact hole. As a result, it is possible to manufacture a semiconductor device having uniform contact resistance over the surface of the semiconductor substrate, irrespective of topology of a lower interconnection layer or the degree of flatness of the interlayer insulating layer covering the lower interconnection layer.

Semiconductor device with contacts having uniform contact resistance and method for manufacturing the same

A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than the width of the bitline.

Semiconductor device with gate space of positive slope and fabrication method thereof

A method for manufacturing a semiconductor device, the method includes the steps of forming an n-type well and a p-type well under a surface of a semiconductor substrate, forming a pad oxide layer having a first thickness on the p-type well and a second thickness on the n-type well, the first thickness being greater than the second thickness, and forming a field oxide layer between the n-type well and the p-type well, the field oxide layer having less bird's beak on the n-type well than on the p-type well.

Method for manufacturing semiconductor device

A method of fabricating a capacitor of a semiconductor memory device includes the steps of: forming an interlevel insulating layer on a semiconductor substrate on which the capacitor will be formed, selectively etching a portion of the interlevel insulating layer placed on a capacitor forming portion to form a capacitor node hole, and forming a first temporary layer on the interlevel insulating layer, including a portion of the interlevel insulating layer in which the capacitor node hole is formed; forming a contact hole beneath the capacitor node hole in a capacitor contact portion; forming a conductive layer on the first temporary layer to bury the contact hole and the capacitor node hole, and then forming a second temporary layer on the conductive layer; etching back the second temporary layer through anisotropic etching process to expose the conductive layer, and to simultaneously form a temporary pillar layer inside the capacitor node hole, the temporary pillar layer being substantially surrounded by the conductive layer; removing a portion of the conductive layer placed on a portion other than the capacitor forming portion, to form a first capacitor electrode and to expose at least a portion of the first temporary layer; and removing remaining portions of the first and second temporary layers to expose an upper portion of the first capacitor electrode, forming a dielectric layer on a surface of the first capacitor electrode, and forming a second capacitor electrode on a surface of the dielectric layer.

Growing community of inventors

Seoul, South Korea

Mun-Mo Jeong