International Business Machines Corporation

Mukta S Farooq

Robert Anthony Rita

John Ulrich Knickerbocker

Eric D Perfecto

George E White

Herbert I Stoller

Harvey Charles Hamel

Sudipta Kumar Ray

Shaji Farooq

Raymond A Jackson

Suryanarayana Kaja

Srinivasa S Reddy

Vincent P Peterson

Kathleen M Wiley

Roy Rongqing Yu

Laertis Economikos

Stephen Mark Rossnagel

David Edward Kotecki

Mark J LaPlante

Thomas Anthony Wassick

Sarah Huffsmith Knickerbocker

Lewis Sigmund Goldmann

Chandrika Prasad

Anson Jay Call

Michael F McAllister

Madhavan Swaminathan

Rajesh S Patel

Paul F Bodenweber

Yuet-Ying Yu

Ajay Prabhakar Giri

Mark G Courtney

Ananda H Kumar

Srinivasa S N Reddy

George Czornyj

Charles J Hendricks

Srinivasa N Reddy

Gregory Blair Martin

Keshav B Prasad

Stephen Anthony DeLaurentis

Terence W Spoor

Kenneth Chang

Philo B Hodge

Ralph R Comulada

Heinz O Steimel

Marvin S Pitler

The distance between a discrete or passive electrical component and an electrical semiconductor device and substrate or carrier is minimized by shortening the lead length connections of the passive component. One or more passive electronic components are mounted within the body of a carrier or board by creating a cavity in the substrate or carrier that is directly below a semiconductor device. The passive component is electrically connected to the substrate and device using solder bump technology resulting in much shorter lead length connections to and from the passive component.

Multi-cavity substrate structure for discrete devices

A process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.

Decoupling capacitor method and structure using metal based carrier

A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

Thin film wiring scheme utilizing inter-chip site surface wiring

A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.

High k dielectric material with low k dielectric sheathed signal vias

The capacitor on a ceramic substrate one by unique film metallization including in one embodiment an in situ oxidation of titanium to create a metal oxide capacitor. The combination of metals when used with the appropriate optimized oxidation conditions and parameters ensures a high yielding capacitor with high capacitance in absence of noble metals and with ease of manufacture providing a low cost, high yield capacitor on ceramic.

Thin film capacitor on ceramic

The present invention relates generally to a new structure and method for chip burn-in and/or testing. More particularly, the invention encompasses a baseplate that is secured to a delicate chip and a method for such an invention is also disclosed. The inventive baseplate provides an added strength to a complex chip while it is being tested and/or burned-in, and then during normal use the baseplate of this invention is an integrated component of the chip.

Baseplate for chip burn-in and/of testing, and method thereof

The present invention relates generally to an electrical interconnection package and a method thereof. More particularly, the invention encompasses an invention that increases the fatigue life of a Ball Grid Array (BGA) electrical interconnection. This invention structurally couples at least one module to an organic interposer using a high modulus underfill material. The organic interposer is then joined to a organic board using standard joining processes. The inventive module can then be removed from the organic board at any time by moving the organic interposer using standard rework techniques.

Electrical interconnection package and method thereof

Disclosed is an interposer and test structure for making contact between a substrate and a test bed. One embodiment of the interposer has a floating, rigid conductive element in a nonconductive body which makes temporary contact between the test bed and the substrate. In another embodiment of the invention, the interposer includes two layers of material, in which one layer includes pogo pins for contacting the substrate and the other layer includes pads for contacting the test bed. The pogo pins are on a grid spacing corresponding to that of the substrate input/output pads while the interposer pads are on a grid spacing corresponding to that of the pogo pin contactors of the test bed.

Interposer for maintaining temporary contact between a substrate and a test bed

A system for locating electrically conductive contact points on an integrated circuit semiconductor substrate utilizes capacitance and line continuity measurements to control and direct the movement of a two-point probe tester in order to locate and precisely align each test probe with designated contact points. The system is capable of testing for continuity conditions or defects and perform other related electrical measurements.

Search routine for 2-point electrical tester

A device and method for enabling the reworkability of an integrated circuit comprising a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.

Reworkability method for wirebond chips using high performance capacitor

An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 mm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer is comprised of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 mm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.

Method for a thin film multilayer capacitor

Method for making high k dielectric material with low k dielectric sheathed signal vias

A multilayer ceramic substrate having a thin film structure containing capacitor connected thereto is provided as an interposer capacitor, the capacitor employing platinum as the bottom electrode of the capacitor. In a preferred capacitor, a dielectric material such as barium titanate is used as the dielectric material between the capacitor electrodes. The fabrication of the interposer capacitor requires an in-situ or post deposition high temperature anneal and the use of such dielectrics requires heating of the capacitor structure in a non-reducing atmosphere. A layer of a high temperature, thin film diffusion barrier such as TaSiN on the lower platinum electrode between the electrode and underlying multilayer ceramic substrate prevents or minimizes oxidization of the metallization of the multilayer ceramic substrate to which the thin film structure is connected during the fabrication process. A method is also provided for fabricating an interposer capacitor with a multilayer ceramic substrate base and a thin film multilayer structure having at least one capacitor comprising at least one bottom platinum electrode.

High temperature, conductive thin film diffusion barrier for ceramic/metal systems

High k dielectric capacitor with low k sheathed signal vias

Growing community of inventors

Hopewell Junction, NY, United States of America

Mukta S Farooq