International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Ultratech, Inc.

Mukta G Farooq

John Anthony Fitzsimmons

Kevin Shawn Petrarca

Emily R Kinser

Richard Paul Volant

Robert Hannon

Ian D Melville

Subramanian Srikanteswara Iyer

John Ulrich Knickerbocker

Katsuyuki Sakuma

Anthony K Stamper

Steven John Koester

Spyridon Skordas

Frank Louis Pompeo

James John Kelly

Roy Rongqing Yu

Kangguo Cheng

Huilong Zhu

Sampath Purushothaman

Richard Stephan Wise

Timothy Dooling Sullivan

Fen Chen

Ruilong Xie

Fei Liu

Xiao Hu Liu

Albert M Young

William E Bernier

Chih-Chao Yang

Louis L Hsu

Zhijiong Luo

Ping-Chuan Wang

Louis Lu-Chen Hsu

Zhengwen O Li

Thomas M Shaw

Roger Allan Quon

Krystyna Waleria Semkow

Jeffrey P Gambino

Timothy Joseph Dalton

Michael A Gaynes

David Clifford Long

Andrew Herbert Simon

Da-Yuan Shih

Benjamin V Fasano

David L Edwards

Wei Lin

Eric D Perfecto

Sudipta Kumar Ray

Mario John Interrante

Krishna R Tunga

Lawrence Alfred Clevenger

Carl John Radens

Haining S Yang

Balasubramanian Pranatharthiharan

Keith Kwong Hon Wong

Mark David Jaffe

Kenneth Parker Rodbell

Arvind Kumar

Paul Stephen Andry

Peter Alfred Gruber

Chandrasekharan Kothandaraman

Hilton T Toy

Erdem Kaltalioglu

Randy Lee Wolf

Michael Wayne Lane

Lewis Sigmund Goldmann

Brent A Anderson

Junli Wang

Michael Shur

Daniel C Edelstein

Ramachandra Divakaruni

Dechao Guo

Julien Frougier

Evan G Colgan

Takeshi Nogami

Timothy Harrison Daubenspeck

Wolfgang Sauter

Zhong-Xiang He

Christopher David Muzzy

Jae-Woong Nah

Eren Kursun

Herbert Lei Ho

Laertis Economikos

Kisik Choi

Brian Joseph Greene

Ravi Nair

Joshua M Rubin

Kamal Kumar Sikka

Stephen Mark Rossnagel

Stuart A Sieg

Bipin Rajendran

Sung Kwon Kang

Bruce Kenneth Furman

Michael P Belyansky

Cornelia K Tsang

Jin Ping Liu

Subhash Laxman Shinde

Steven Paul Ostrander

Qianwen Chen

Tao Li

H Bernhard Pogge

A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

Resist patterned redistribution wiring on copper polyimide via layer

An approach for forming semiconductor structure composed of one or more stacked semiconductor devices with a first semiconductor device on a substrate, a first interconnect wiring structure over the first semiconductor device, a second interconnect wiring structure under a second semiconductor device joined to the first interconnect wiring structure, and a third interconnect wiring structure on the second semiconductor device where the first semiconductor device and the second semiconductor device are each one of a memory device or a logic device. The approach includes each of the first interconnect wiring structure, the second interconnect wiring structure, and the third interconnect wiring structure with a contact pitch to the first semiconductor device and to both sides of the second semiconductor device that is less than one hundred nanometers.

Stacked semiconductor devices with topside and backside interconnect wiring

A method for fabricating a dual redistribution layer (RDL) interposer structure is provided. The method includes etching a semiconductor substrate to expose natural crystallographic planes to form trenches. The method also includes depositing conductive material within the trenches of the etched semiconductor substrate to form vias for an interposer structure. The method includes placing back end of line (BEOL) inter-chip wiring on a top side of the interposer structure using a first RDL. The method includes exposing the vias on a back side of the interposer structure. The method further includes forming power RDLs on a back side of the interposer structure using conductive lines in a dielectric layer.

Dual redistribution layer structure

A semiconductor device includes an electronic circuit within a device layer; wherein the device layer is between a thin layer of wiring for signal connections having a first thickness and a thick layer of wiring for power having a second thickness, the second thickness being greater than the first thickness; a silicon layer above the device layer, the thin layer of wiring, and the thick layer of wiring; a first via connection from a top of the semiconductor device to the thin layer of wiring; a second via connection from the top of the semiconductor device to the thick layer of wiring; and a packaging substrate with a connection to the thick layer of wiring.

TSV and backside power distribution structure

A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

Infrared debond damage mitigation by copper fill pattern

An approach to provide a method of joining a semiconductor chip to a semiconductor substrate, the approach includes depositing a nanoparticle paste and aligning each of one or more solder contacts on a semiconductor chip to a substrate bond pad. The approach includes sintering, in a reducing gaseous environment, the nanoparticle paste to connect the semiconductor chip to a semiconductor substrate bond pad.

Sintering a nanoparticle paste for semiconductor chip join

A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.

Substrate thinning for a backside power distribution network

A semiconductor structure includes a power distribution network including a first buried power rail, a power wire, and a first buried via electrically interconnecting the first buried power rail and the power wire. Each of the first buried power rail, the power wire, and the first buried via have a liner on a corresponding bottom surface thereof and sidewalls thereof. The structure also includes a dielectric layer outward of the power distribution network; a first field effect transistor outward of the dielectric layer; a first via trench contact electrically interconnecting a source/drain region of the transistor to the first buried power rail; a first outer wire outward of the first field effect transistor; and an electrical path electrically interconnecting the first outer wire with the power wire.

Semiconductor device with early buried power rail (BPR) and backside power distribution network (BSPDN)

An interconnect for a semiconductor device includes a laminate substrate; a first plurality of electrical devices in or on a surface of the laminate substrate; a redistribution layer having a surface disposed on the surface of the laminate substrate; a second plurality of electrical devices in or on the surface of the redistribution layer; and a plurality of transmission lines between the first plurality of electrical devices and the second plurality of electrical devices. The surface of the laminate substrate and the surface of the redistribution layer are parallel to each other to form a dielectric structure and a conductor structure.

High density interconnection and wiring layers, package structures, and integration methods

A semiconductor device including a hybrid contact scheme for stacked FET is disclosed with integration of a BSPDN. A double-sided (both frontside and backside of the wafer) contact scheme with buried power rail (BPR) and backside power distribution network (BSPDN) provides optimum contact and interconnect. The stacked FET could include, for example, FINFET over FINFET, FINFET over nanosheet, or nanosheet over nanosheet.

Stacked FET integration with BSPDN

A semiconductor die package that has a substrate with one or more substrate layers with one or more substrate connections. A substrate layer can include one or more redistribution layers (RDLs). One or more dies (e.g., multiple dies) are disposed on a top substrate layer. The dies have one or more die external connections. Some of the die external connections are electrically connected to one or more substrate connections. One or more metallic dam stiffeners form into a dam enclosure that is disposed on and physically connected to the top substrate layer. The dam enclosure encloses one or more of the dies. The metallic dam enclosure has one or more electrically connected regions where the metallic dam enclosure is electrically connected to one or more of the substrate horizontal connections and one or more electrically insulated regions where the metallic dam enclosure is electrically insulated from one or more of the substrate horizontal connections and the substrate via connections. In different embodiments, the dam enclosure stiffens the substrates/package during manufacture, assembly, and operation; provides confinement for underfill application; and provides a heat conduction path for heat removal. Methods of manufacturing and assembling the die package are disclosed.

Multiple die assembly

A semiconductor device and formation thereof. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a plurality of pillars interconnecting the first semiconductor structure and the second semiconductor structure. The plurality of pillars include a first solder layer and a second solder layer, wherein the first solder layer has a higher melting point than the second solder layer.

Temperature hierarchy solder bonding

Techniques for interconnecting chips using a bridge chip having through vias is provided. In one aspect, a structure includes: a bridge chip attached to at least a first chip and a second chip, wherein the bridge chip has at least one conductive through via connecting the bridge chip to one of the first chip and the second chip. The bridge chip can include a wiring layer having metal lines present between a first capping layer and a second capping layer, and the at least one conductive through via can directly contact at least a sidewall of at least one of the metal lines. A method of integrating chips using the present bridge chip is also provided.

Bridge chip with through via

An exemplary method includes at a bonding temperature, bonding a semiconductor chip to an organic laminate substrate using solder; without cooldown from the bonding temperature to room temperature, at an underfill dispense temperature, dispensing underfill between the semiconductor chip and the organic laminate substrate; and curing the underfill within a range of temperatures above the underfill dispense temperature. Another exemplary method includes depositing a first solder on pads of an organic laminate substrate; contacting a second solder on pillars of a semiconductor chip to the first solder on the pads of the organic laminate substrate; and solder bonding the semiconductor chip to the organic laminate substrate.

Assembly of a chip to a substrate

The present invention discloses embodiments of a semiconductor chip with one or more bottom external (power or ground) connections, a front side power network layer, a device layer, and a grind side power network layer. The device layer has a plurality of devices. One or more of the devices has one or more device power connections and one or more device ground connections and the device layer has a front side and a back grind side. The front side power network layer has power, ground, signal, and other connections that connect to respective device power and device ground connections from/through the top front side layer. In like manner, power, ground, signal, and other connections connect to respective device power and device ground connections from/through the bottom of grind side power network layer. (Alternative, e.g., external conduit connections are disclosed.) Accordingly, one or more first device power connections is connected to one or more of the front side power network layer connections, one or more second device power connections is connected to one or more of grind side power network connections so the front side power network layer and the grind side power network layer provide the device layer with a dual power/ground feed/distribution from both the top/back and bottom/front of the device layer of the chip.

Semiconductor circuit power delivery

Growing community of inventors

Hopewell Junction, NY, United States of America

Mukta G Farooq