Lsi Logic Corporation

Lsi Corporation

Lst Corporation

Mukesh K Puri

Ghasi R Agrawal

V Swamy Irrinki

William D Schwarz

Jun Zhao

Tuan L Phan

Thompson W Crosby

A BISR mode and associated method for testing memory. All redundant elements of the memory including the ones which are not used are tested, and interaction between redundant elements of the memory and adjacent functional memory are checked. Repair information is used to repair the memory. In addition, redundant elements which are not needed to be used for repairing the memory are forced to be used, such as by faking defects to remap good elements with redundant elements.

BISR mode to test the redundant elements and regular functional memory to avoid test escapes

A BISR scheme which provides for on-chip assessment of the amount of repair on a given memory and for the flagging of any device as a fail when the device exceeds a pre-determined limit. Preferably, a counter is built and loaded through a test pattern during production testing, and the counter establishes the threshold for pass/fail criteria. The BISR is configured to load a repair solution and then test the memories for any additional failures and if there are any, repair them (provided enough redundant elements are available). In addition, a reliability controller for BISR designs can be provided, where the reliability controller contains a register set and a number of counters at the chip-level which can be loaded through a test pattern during production tests, where one of the counters contains the number of memories to be allowed for repair.

Hard BISR scheme allowing field repair and usage of reliability controller

A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.

Method and system for performing built-in-self-test routines using an accumulator to store fault information

Method and system for performing built-in self-test routines using an accumulator to store fault information

A semiconductor memory testing implementation suitable for build-in self repair (BISR) memories provides, in one embodiment, a memory testing circuit configuration including an output register for receiving digital data. A plurality of shift registers serially output the digital data to be received by the output register. Each one of the plurality of shift registers includes a feedback path for enabling the digital data output by a corresponding one of the plurality of shift registers to be input back into the corresponding shift register in a same sequence as the digital data is output from the corresponding shift register.

Testing implementation suitable for built-in self-repair (BISR) memories

A method for testing semiconductor devices advantageously increases manufacturing yields. The method includes generating memory repair data for a wafer die by writing at least one predetermined digital bit pattern into a memory on the wafer die, reading the at least one predetermined digital bit pattern back out of the memory, comparing the at least one predetermined digital bit pattern read out from the memory against the at least one predetermined digital bit pattern written into the memory, and storing results of the comparison as the memory repair data. The writing and reading are performed a plurality of times, each time with a different voltage and clock frequency combination being applied to the wafer die. The memory repair data is programmed into the wafer die, and the wafer die is assembled into a packaged semiconductor device. The packaged semiconductor device is tested by causing the memory repair data programmed within the packaged semiconductor device to be transferred into the memory a plurality of times, each time with a different voltage and clock frequency combination being applied to the packaged semiconductor device.

Method for testing semiconductor devices having built-in self repair (BISR) memory

A system and method for protecting the values stored in a BISR repair block and, optionally, debugging the BISR repair logic without altering normal test flow is implemented by a circuit including a plurality of soft latches within the BISR repair block, the soft latches being coupled together to form a BISR scan chain for holding BISR repair information. A chip level scan enable signal and a scan hold control signal cooperate to control connection of the BISR scan chain to other scan chains during a scan test, so that the BSR repair information is held within the soft latches. A diagnose enable signal cooperating with the chip level scan enable signal and the scan hold control signal for enabling debugging of logic connecting the BISR scan chains.

Scan method for built-in-self-repair (BISR)

A BISR scheme which provides that fuse blocks are shared between memories to reduce hard-BISR implementation costs. The scheme includes a plurality of memories serially connected to a fuse controller. A plurality of fuse blocks are also serially connected to the fuse controller. There are more memory instances than there are fuse blocks, and the fuse controller is configured to allow the fuse blocks to be shared between memories. Preferably, each fuse block includes fuse elements which can be programmed with the memory instance number which needs to be repaired. The fuse block reduces routing congestion and is preferably configured to provide the flexibility of assigning any fuse block to any instance that needs repair. The programmable fuse elements are preferably loaded into a counter (which is preferably part of the fuse controller) which ensures that the correct block information gets loaded into the corresponding memory instance.

Sharing fuse blocks between memories in hard-BISR

An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.

Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories

An efficient and reliable technique is disclosed for detecting faults which occur in FIFO's, including control faults which are specific to FIFO's, as well as faults common to conventional memories, such as interport faults and faults that occur in single port memories. The technique utilizes a sequence of read, write and control operations, thereby avoiding the need to directly observe internal values within the FIFO, such as the full and empty flag values and the shift register values.

Detecting faults in dual port FIFO memories

A multiport testing procedure capable of detecting faults that occur between static random access memory ports as well as traditional cells faults uncovers all possible faults and covers all cells in the memory, without placing architectural constraints on the memory. While executing a test sequence on one port of the memory array, concurrent memory accesses are performed through other ports in the memory. If a fault exists between the port under test and any other port, then the concurrent operations interfere with the values read and/or written on the port under test, and the test uncovers the fault. Thus, for any one test port, the interport test requires only as many memory operations as the associated single port test, keeping test time to a minimum. One embodiment detects faults between the test port, which is a read/write port, and any other port, including read ports and write ports, comprising six passes through the memory. Another embodiment detects faults between write ports, comprising four memory passes. An embodiment of a memory test circuit is disclosed that executes the multiport tests.

Detecting interport faults in multiport static memories

A CAM testing procedure detects storage logic faults, comparison logic faults, and faults caused by interactions between the storage and comparison logic for both single port and dual port CAM's. To uncover faults in the storage logic, a series of read and write operations are performed, either using a standard test sequence, such as the March C algorithm, or any other desired test sequence. The CAM test, however, intermixes comparison operations with the read and write operations to uncover faults in the comparison logic. For dual port memories, the test sequence comprises executing comparison operations concurrently with the read and/or write operations, thus revealing faults between the storage and comparison logic. For single port memories, the test sequence comprises performing a comparison operation following the read/write operations at each address, immediately verifying the comparison logic at each address.

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Fremont, CA, United States of America

Mukesh K Puri