Georgia Tech Research Corporation

University of California

Wayne State University

Muhannad S Bakir

James D Meindl

Paul Albert Kohl

Kevin P Martin

Chirag Suryakant Patel

Thomas K Gaylord

Hollie K Reed

Elias N Glytsis

Stephen M Schultz

Tony Mule′

Tony Mule&prime;

Calvin Richard King, Jr

Deepak Chandra Sekar

Andrew C Kummel

Charles H Winter

Hiren D Thacker

Jonathan Hollin

Victor Wang

Todd Spencer

Paul Kim Jo

Jesal Zevari

Gang Huang

Paragkumar Thadesar

Ricardo Villalaz

Bing Dang

Nyi Myat Khine Linn

Ate He

Mike Breeden

Ramasamy Ravindran

Mark Cupta

Ming-Jui Li

Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.

Methods of forming stacked integrated circuits using selective thermal atomic layer deposition on conductive contacts and structures formed using the same

Disclosed are various embodiments that involve mechanically flexible interconnects, methods of making mechanically flexible interconnects, methods of using mechanically flexible interconnects, and the like.

Mechanically flexible interconnects, methods of making the same, and methods of use

Disclosed are a variety of mixed-signal substrates comprising a plurality of photo-defined through substrate vias and methods of making the same. In an embodiment, a mixed-signal substrate can comprise a plurality of trenches embedded in a substrate, a photodefineable polymer within at least a portion of each trench, the photodefineable polymer defining one or more channels within each of the plurality of trenches, and a conductive material filling at least a portion of the one or more channels within the photodefineable polymer to form one or more through substrate vias. The photo-defined through substrate vias can comprise a variety of arrangements, numbers of vias, shapes, and dimensions across a single substrate.

Mixed-signal substrate with integrated through-substrate vias

Exemplary embodiments of the present invention disclose a modular testing assay. According to various embodiments of the present invention, the sensor arrays, or microplates, are removably attached to a substrate. In some embodiments, the electrical connection between the sensors of the sensor array and the substrate provide for the removal of one sensor array or microplate with another or similar sensor array. The sensor arrays can be aligned using various types of alignment devices or the substrate can be configured to allow various alignments and spatial orientations of one or more sensor arrays.

Modular nano and microscale sensors

An exemplary embodiment of the present invention provides a chip for use in fabricating a three-dimensional integrated circuit, the chip comprising a wafer, one or more metallic-filled, electrical vias, and one or more hollow, fluidic vias. The wafer can comprise a first surface and a second surface. The one or more metallic-filled, electrical vias can extend through the wafer. Each electrical via can be in electrical communication with an electrical interconnect proximate the first surface, providing electrical communication between chips in the integrated circuit. The one or more hollow, fluidic vias can extend through the wafer. Each fluidic via can be in fluid communication with a fluidic interconnect, providing fluid communication between adjacent chips in the integrated circuit. Each fluidic interconnect can comprise a first end proximate the first surface, a second end, and a cap proximate the second end, defining an air-filled space within the fluidic interconnect.

Air-gap C4 fluidic I/O interconnects and methods of fabricating same

Three dimensional integrated circuits with double sided power, coolant, and data features and methods of constructing same are provided. According to some embodiments, an integrated circuit package can generally comprise one or more semiconductor wafers and opposing end substrates. The semiconductor wafers can each have a top exterior surface and a bottom exterior surface. The plurality of semiconductor wafers can form a multi-dimensional wafer stack of die wafers such that adjacent wafers have facing surfaces. Each of the semiconductor wafers can comprise one or more channels formed through the wafers. A portion of the channels can extend generally between the top and bottom exterior surfaces of the semiconductor wafers. A portion of the channels can carry conductors for coupling the wafers and/or coolant for cooling the wafers. The opposing end substrates can be disposed proximate opposing ends of the multi-dimensional stack. The opposing end substrates can be configured to supply power, coolant, and data signals to opposing ends of the multi-dimensional wafer stack. Other embodiments are also claimed and described.

3-D ICs equipped with double sided power, coolant, and data features

Three dimensional integrated circuits with microfluidic interconnects and methods of constructing same are provided. According to some embodiments, and microfluidic integrated circuit system can comprise a plurality of semiconductor die wafers each having a top and bottom exterior surface. The semiconductor die wafers can form a stack of die wafers. The die wafers can comprise one or more channels formed through the die wafers. The channels can extend generally between top and bottom exterior surfaces of the semiconductor die wafers. A plurality of micro-pipes can be disposed between adjacent semiconductor die wafers in the stack. The micro-pipes can enable the channels to be in fluid communication with each other. A barrier layer can be disposed within at least one of the channels and the micro-pipes. The barrier layer can be adapted to prevent a coolant flowing through the at least one of the channels and the micro-pipes from leeching into the channels and micro-pipes. Other embodiments are also claimed and described.

3-D ICs with microfluidic interconnects and methods of constructing same

High performance interconnect devices, structures, and fabrication methods are provided herein. According to some embodiments of the present invention, an interconnect device used to connect components or route signals in an integrated circuit can comprise multiple conductors. A first conductor of the interconnect device can define a first conductor axis, and a second conductor of the interconnect device can define a second conductor axis. The second conductor can be proximate the first conduct such that first conductor axis is substantially coaxially situated relative to the second conductor axis to provide a high performance interconnect having a coaxial alignment. The first conductor and the second conductor can define a gap disposed between and separating the conductors. Other embodiments are also claimed and described.

Integrated circuit interconnects with coaxial conductors

Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.

High input/output density optoelectronic probe card for wafer-level test of electrical and optical interconnect components, methods of fabrication, and methods of use

Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed of a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.

Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof

Input/output (I/O) interconnects, fluidic I/O interconnects, electrical, optical, and fluidic I/O interconnects, devices incorporating the I/O interconnects, systems incorporating the I/O interconnects, and methods of fabricating the I/O interconnects, devices, and systems, are described herein.

Microfluidic, optical, and electrical input output interconnects, methods of fabrication thereof, and methods of use thereof

Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.

Devices and methods of fabrication thereof are disclosed. A representative device includes a complaint wafer-level package having one or more lead packages. A representative lead package includes a substrate having a plurality of die pads disposed thereon and a plurality of leads attached to the plurality of die pads. In addition, the lead package includes a plurality of pillars made of a low modulus material. Each pillar is disposed between the substrate and at least one lead, and each lead is disposed upon one of the pillars that compliantly support the lead.

Devices having compliant wafer-level packages with pillars and methods of fabrication

Devices and systems having one or more of the following components: a compliant pillar with a modified tip surface (non-flat tip) and a corresponding compliant socket; an optical/electrical I/O interconnect and a corresponding compliant socket; a lens/waveguide optical pillar, a polymer bridge, and an L-shaped pillar, are described herein. In addition, methods of making these components and methods of using these components are disclosed herein.

Dual-mode/function optical and electrical interconnects, methods of fabrication thereof, and methods of use thereof

Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.

Growing community of inventors

Atlanta, GA, United States of America

Muhannad S Bakir