Agere Systems Inc.

Lucent Technologies Inc.

At+t Corp.

At&t Bell Laboratories

Other

Agere Systems Guardian Corp.

Ciclon Semiconductor Device Corp.

Aqere Systems Guardian Corp.

Muhammed Ayman Shibib

Shuming Xu

Zhijian Xie

Isik C Kizilyalli

Peter Ledel Gammel

Charles Walter Pearce

Frank Alexander Baiocchi

Bailey R Jones

Marco Mastrapasqua

Milton L Embree

Adrian R Hartman

John Michael Hergenrother

John Charles Desko

Hans W Becke

Robert K Smith

John C Gammel

An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Metal-oxide-semiconductor device having trenched diffusion region and method of forming same

In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimize the amount of hot-carrier injection degradation while maintaining a breakdown voltage in the device which is greater than or equal to a prescribed value.

Control of hot carrier injection in a metal-oxide semiconductor device

An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.

Dual-gate metal-oxide-semiconductor device

A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and second source/drain regions of the second conductivity type in the second layer proximate the upper surface of the second layer, the first source/drain region being spaced laterally from the second source/drain region, the gate being formed at least partially between the first and second source/drain regions; and forming at least one electrically conductive trench in the second layer between the gate and the second source/drain region, the trench being formed proximate the upper surface of the semiconductor layer and extending substantially vertically through the second layer to the substrate. The step of forming the trench includes the steps of forming an insulating layer substantially lining sidewalls of the trench, and substantially filling the trench with an electrically conductive material.

Metal-oxide-semiconductor device having improved performance and reliability

Dual-gate metal-oxide semiconductor device

An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.

Metal-oxide-semiconductor device including a buried lightly-doped drain region

An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region. The shielding structure is configured such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of an amount of coverage of the shielding structure over an upper surface of the drift region.

An electrostatic discharge (ESD) protection circuit for protecting a circuit from an ESD event, the ESD protection circuit comprises a metal-oxide semiconductor (MOS) device including a gate terminal, a first source/drain terminal, a second source/drain terminal and a bulk terminal, the bulk and first source/drain terminals being operatively coupled across the circuit to be protected, the gate and second source/drain terminals being coupled together; and a voltage generation circuit coupled between the bulk and gate terminals of the MOS device. The voltage generation circuit is configured to generate a voltage difference between the bulk and gate terminals of the MOS device during at least a portion of the ESD event. In this manner, a current handling capability of the MOS device is increased, thereby advantageously enabling a smaller sized device having a significantly smaller capacitance associated therewith to be employed in the ESD protection circuit.

Electrostatic discharge protection in a semiconductor device

An MOS device comprises a semiconductor layer of a first conductivity type and source and drain regions of a second conductivity type formed in the semiconductor layer, the source and drain regions being spaced apart from one another. A drift region is formed in the semiconductor layer proximate an upper surface of the semiconductor layer and between the source and drain regions, and a insulating layer is formed on the semiconductor layer above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the source and drift regions. The MOS device further includes a conductive structure comprising a first end formed on the insulating layer and spaced apart from the gate, and a second end formed on the insulating layer and extending laterally toward the drain region above at least a portion of the drift region. The conductive structure is configured such that a thickness of the insulating layer under the second end of the conductive structure increases as the second end extends toward the drain region.

Graded conductive structure for use in a metal-oxide-semiconductor device

An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.

Metal-oxide-semiconductor device with enhanced source electrode

An MOS device includes a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane. First and second source/drain regions are formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A gate is formed proximate the upper surface of the semiconductor layer and disposed at least partially between the first and second source/drain regions. A first dielectric region is formed in the MOS device, the first dielectric region defining a trench extending downward from the upper surface of the semiconductor layer to a first distance into the semiconductor layer, the first dielectric region being formed between the first and second source/drain regions. The MOS device further includes a shielding structure formed primarily in the first dielectric region, at least a portion of the shielding structure being disposed adjacent a bottom wall of the first dielectric region and/or one or more sidewalls of the first dielectric region.

Metal-oxide-semiconductor device having an enhanced shielding structure

A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close relative proximity to one another, and oxidizing the semiconductor layer such that an insulating layer is formed on at least sidewalls and bottom walls of the trenches. The trenches are configured such that the insulating layer formed as a result of the oxidizing step substantially fills the trenches and substantially consumes the semiconductor layer between corresponding pairs of adjacent trenches. In this manner, a substantially continuous oxide region is formed throughout the plurality of trenches.

Thick oxide region in a semiconductor device

A technique for forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on a least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench in an upper surface of the semiconductor wafer and partially into the epitaxial layer. The method further includes the step of forming at least one diffusion region between a bottom wall of the trench and the substrate, the diffusion region providing an electrical path between the bottom wall of the trench and the substrate. One or more sidewalls of the trench are doped with a first impurity of a known concentration level so as to form an electrical path between an upper surface of the epitaxial layer and the at least one diffusion region. The trench is then filled with a filler material.

Enhanced substrate contact for a semiconductor device

An MOS device includes a semiconductor layer comprising a substrate of a first conductivity type and a second layer of a second conductivity type formed on at least a portion of the substrate. First and second source/drain regions of the second conductivity type are formed in the second layer proximate an upper surface of the second layer, the second layer being spaced laterally from the first source/drain region. A gate is formed above the second layer proximate the upper surface of the second layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one electrically conductive trench formed in the second layer between the gate and the second source/drain region, the trench being formed proximate the upper surface of the semiconductor layer and extending substantially vertically through the second layer to the substrate. The MOS device exhibits reduced HCI effects and/or improved high-frequency performance.

Growing community of inventors

Wyomissing, PA, United States of America

Muhammed Ayman Shibib