Taiwan Semiconductor Manufacturing Comp. Ltd.

Mu-Yi Lin

Kuang-Hsin Chen

Bor-Zen Tien

Tzong-Sheng Chang

Hsuan-Han Lin

Jhu-Ming Song

Yu-Hua Lee

Tzy-Kuang Lee

Chin-Tien Yang

Yu-Wei Tseng

Min Ca

Chia-Chou Tsai

An apparatus includes a plurality of interconnect structures over a substrate, a dielectric layer formed over a top metal line of the plurality of interconnect structures, a first barrier layer on a bottom and sidewalls of an opening in the dielectric layer, wherein the first barrier layer is formed of a first material and has a first thickness, a second barrier layer over the first barrier layer, wherein the second barrier layer is formed of a second material different from the first material and has a second thickness and a pad over the second barrier layer, wherein the pad is formed of a third material.

Method for forming interconnect structure

Fuse structures and forming and operation methods thereof are disclosed. One of the fuse structures includes a dielectric strip and a fuse strip extending in different directions. The dielectric strip is sandwiched by a first conductive strip and a second conductive strip. The fuse strip is insulated from each of the first conductive strip and the second conductive strip and has a blowing region corresponding to the dielectric strip.

Fuse structures and forming and operation methods thereof

A method comprises forming a plurality of interconnect components over a gate structure, wherein a bottom metal line of the interconnect components is connected to the gate structure through a gate plug, depositing a dielectric layer over a top metal line of the interconnect components, forming an opening in the dielectric layer, depositing a first barrier layer on a bottom and sidewalls of the opening using a non-plasma based deposition process, depositing a second barrier layer over the first barrier layer using a plasma based deposition process and forming a pad in the opening.

A method for forming interconnect structures comprises forming a metal line made of a first conductive material over a substrate, depositing a dielectric layer over the metal line, patterning the dielectric layer to form an opening, depositing a first barrier layer on a bottom and sidewalls of the opening using an atomic layer deposition technique, depositing a second barrier layer over the first barrier layer, wherein the first barrier layer is coupled to ground and forming a pad made of a second conductive material in the opening.

A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

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Taichung, Taiwan

Mu-Yi Lin