Samsung Electronics Co., Ltd.

Mu-Hui Park

Beak-Hyung Cho

Woo-Yeong Cho

Kwang-Jin Lee

Wooyeong Cho

Hee-Won Kim

Ji-Young Lee

Yeong-taek Lee

Hye-Jin Kim

Dae-seok Byeon

Hyung-Rok Oh

Sang-beom Kang

Young-Don Choi

Yoon-Hee Choi

Hyun-Kook Park

Cheon An Lee

Jiho Cho

Ickhyun Song

A three-dimensional semiconductor memory device includes first to third cell array layers sequentially stacked on a substrate. Each of the first to third cell array layers includes memory cells arranged along first and second directions crossing each other and parallel to a top surface of the substrate. Each of the memory cells includes a variable resistance element and a tunnel field effect transistor connected in series. The device further includes bit lines extending along the first direction between the first and second cell array layers and at least one source line extending along either the first direction or the second direction between the second and third cell array layers. The memory cells of the first and second cell array layers share the bit lines, and the memory cells of the second and third cell array layers share the source line.

Three-dimensional semiconductor memory devices

A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.

Method of operating resistive memory device reducing read disturbance

A method of operating a nonvolatile memory device is provided as follows. The nonvolatile memory device includes memory blocks each of which has word lines. A setup voltage is applied to the word lines. A word line voltage is applied to a first word line selected from the word lines. Recovery voltages are applied to the word lines. Each recovery voltage is applied to at least one corresponding word line of the word lines. The recovery voltages have different voltage levels from each other.

Operation method operating nonvolatile memory device having plurality of memory blocks

A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled.

Nonvolatile memory device and method for sensing the same

A resistive memory device comprising: a memory cell having a programmable resistance representing stored data; and a read circuit configured to be connected to the memory cell via a first signal line and read the stored data, wherein the read circuit includes: a voltage controller configured to control a first voltage of the first signal line to be a constant voltage and output a signal to a sensing node; and a sense amplifier connected to the voltage controller via the sensing node, and configured to compare a sensing voltage of the sensing node with a reference voltage.

Resistive memory device and memory system including resistive memory device

A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and the first resistive memory cell to provide a clamping bias to the first resistive memory cell, a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled.

A method of sensing multi-bit data stored in a resistive memory cell includes; determining a resistive value range for the memory cell by performing a first read operation using a first read voltage and a first reference current, determining whether the multi-bit data stored in the resistive memory cell has a first program state, upon determining that the multi-bit data stored does not have the first program state, selecting a second read voltage different from the first read voltage in response to the resistive value range of the resistive memory cell, and using the second read voltage to again determine whether the multi-bit data stored in the resistive memory cell has the first program state.

Nonvolatile memory device having resistive memory cell and method sensing data in same

Provided is a nonvolatile memory device. The nonvolatile memory device may include a resistive memory cell, a reference current generator which provides a reference current, a reference signal generator which provides a reference signal indicating a reference time for data read based on the reference current, and a read circuit which receives the reference signal and reads data by comparing a ramp-up time of a cell current flowing through the resistive memory cell with the reference time.

Reliable read operation for nonvolatile memory device with resistance material that reads data based on reference current

A sensing circuit includes a plurality of cell read current generators, a reference current generator and a plurality of sense amplifiers. Each of the cell read current generators generates a cell read current from each of a plurality of memory cells. The reference current generator sums the cell read currents to generate a sum current. Each of the sense amplifiers determines data state stored in each of the memory cells based on each of the cell read currents and an average current. The average current is obtained based on the sum current.

Sensing circuits and phase change memory devices including the same

A phase change memory device includes a memory cell array having a plurality of phase change memory cells, a read bias generating circuit, a clamping circuit and a clamping control signal generating circuit (CCSGC). The read bias generating circuit provides a sensing node with a read bias for reading a resistance level of a selected phase change memory cell. The clamping circuit controls an amount of clamping current flowing into a bit line connected with the selected phase change memory cell. The CCSGC provides the clamping control signal to the clamping circuit and adjusts a level of the clamping control signal.

Phase change memory devices and memory systems including the same

A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

Phase change memory device generating program current and method thereof

In a phase-change random access memory (PRAM) device, a write operation is performed by applying a set pulse to failed PRAM cells. The set pulse comprises a plurality of stages sequentially decreasing from a first current magnitude to a second current magnitude. The first current magnitude or the second current magnitude varies from one write loop to another.

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Hwaseong-si, South Korea

Mu-Hui Park