United Microelectronics Corp.

United Silicon Incorporated

Mu-Chun Wang

Shiang Huang-Lu

Tien-Hao Tang

Shih-Chieh Kao

Tzung-Han Lee

Shiao-Shien Chen

Kuan-Yu Fu

Yih-Jau Chang

Yuan-Chang Liu

Shih-Chung Li

Water Lur

Juan-Yuan Wu

Jih-Wen Chou

Sheng-Hsing Yang

Hsueh-Hao Shih

Kun-Cho Chen

Chuan H Liu

Chau-neng Wu

Donald Cheng

Yu-Yiu Lin

An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed in the well region. A second region formed having a portion in the weil region and another portion outside the well region, but still within the semiconductor substrate. Moreover, a third region formed within the well region and in between the first; region and the second region. A fourth region formed within the semiconductor substrate and outside the well region. A fifth region formed within the semiconductor substrate and in between the second region and the fourth region. Furthermore, the second region and the fifth region form the n-pjunction of a zener diode and the breakdown voltage of the zener diode is controlled by adjusting the ion dosage in the second region.

CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection

A device structure and a method of fabricating an electrostatic discharge (ESD) protection circuit on a semiconductor device. A substrate is provided. A layer of silicon oxide is formed on the substrate. A photoresist mask is formed on the layer of silicon oxide. A species of n-type ions is implanted into the surface to form source/drain regions in the ESD protection area. After removing the photoresist, a metal layer is blanket deposited over the surface. A thermal process is performed to form salicide layers on the source/drain regions. A patterned photoresist is respectively formed to cover a portion of the salicide layer. An etching process is performed to strip away the exposed portion of the salicide layer.

Electrostatic discharge protection structure and a method for forming the same

A semiconductor device having an electrostatic discharge protective circuitry adapted to a common discharge line (CDL) is disclosed. In the embodiments of the present invention, semiconductor device includes a plurality of bonding pads, each having at least one connecting terminal, a common discharge line, and a protective device connected between the connecting terminal and the common discharge line. Moreover, the protective device is composed of a silicon-control-rectifier that is used for electrostatic discharge protection and a zener diode for lowering a trigger voltage of the silicon-control-rectifier.

Electrostatic discharge protective circuitry equipped with a common discharge line

A gate dielectric breakdown test method is disclosed. The method includes performing a one step programmed VRDB test using Vcc voltage power source, gate current density for the corresponding ramped voltages are recorded. If the gate current density is found to be higher than a specified gate current density criterion, then the gate oxide is deemed to defective and is scrapped. And, if the gate current density (Jg) is found to be less than the specified gate current density criterion (Jc), then a differential gate current density ratio R&equals;&Dgr;Jg/Jg for the corresponding ramped voltages are calculated. If the R value is found to be less than a specified differential current density ratio criterion (Rc), then the gate dielectric is considered to be robust, and if the R value is greater than the Rc value, then the gate dielectric is considered to be inflected. Accordingly, the voltage Vg can be effectively used for justifying the integrity of the gate dielectric.

Method of determining integrity of a gate dielectric

A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.

Via plug layout structure for connecting different metallic layers

A structure of a cross guard ring along the edge of a semiconductor chip is disclosed. A first guard ring, a second guard ring and a third guard ring are formed along the edge of a semiconductor chip. Each guard ring comprises several rectangle shaped vias which are positioned along the edge of the chip structure, wherein each rectangle via is separated from an adjacent rectangle via by a gap. Further, each rectangle via of the second guard ring is positioned opposite the said gap of the first guard ring and are crossed over and have some overlay with rectangle vias of the first guard ring which are separated by the said gap as shown in FIG. 2. Similarly the third guard ring is positioned with respect to the second guard ring.

Cross guard-ring structure to protect the chip crack in low dielectric constant and copper process

A semiconductor device for preventing process-induced charging damages is disclosed. The semiconductor device comprises a semiconductor layer, at least one transistor comprising a source region, a drain region, a channel region, a gate oxide layer and a gate electrode, at least one parasitic capacitor comprising a conductive layer, a dummy conductive layer constituting a dummy pattern, and a dielectric layer interposed between the conductive layer and the dummy conductive layer, a first conductor connecting the gate electrode and the conductive layer, and a second conductor connecting the semiconductor layer and the dummy conductive layer. Furthermore, the dummy conductive layer can be a floating layer over the semiconductor layer. In such manner, the second conductor set forth is replaced by an interposed dielectric layer.

Semiconductor device for preventing process-induced charging damages

A method for protecting the gate oxide layer of a MOS device. The method can also be used to monitor the intensity of radiation and charged particles falling on the gate oxide layer. The method includes the provision of a substrate having a gate structure thereon and an inter-layer dielectric layer over the gate structure, wherein the gate structure further includes a gate oxide layer and a gate electrode. Thereafter, a shielding layer is formed over the inter-layer dielectric layer, and then a protection diode is formed to link the shielding to the substrate.

Method for protecting gate oxide layer and monitoring damage

A method of fabricating a protection device. A contact resistor, or a protection diode and a contact resistor are formed in a substrate. The protection diode and the contact resistor are electrically connected to a gate of a MOS so as to protect the MOS from being damaged by plasma. A multi-level interconnect is formed on the substrate, while a top metal layer of the multi-level interconnect is patterned, the electrical connection between the gate and the protection device is broken.

Method of fabricating protection structure

A statistical method of monitoring the yield of a gate oxide layer. A voltage is applied to first test keys and second test keys to build curves showing relationship between failure distribution and charge density, wherein each of the first test keys has a first oxide area and each of the second test keys has a second oxide area. A yield of the first test keys and a yield of the second test keys up to a charge density can be obtained. The yields of the first test keys and the second test keys have a relationship as an equation of area. To obtain a yield of small test keys, a yield and area of large test keys are imported into an equation. According to operating the equation, the yield of a small gate oxide is obtained.

Statistical method of monitoring gate oxide layer yield

A method of protecting gate oxide. A chip having a gate thereon is provided. The gate structure comprises a gate oxide layer and a gate electrode. The gate is covered by a dielectric layer. A protection layer is formed on the dielectric layer. The protection layer is pattern to remain a part of the protection layer aligned over the gate.

Method of protecting gate oxide

A method for testing the reliability of a dielectric thin film. An exponential current ramp test is performed with a delay time to test the dielectric thin film. An exponential current ramp charge-to-breakdown distribution, which is represented by cumulative distribution failure percentage, is obtained. An exponential current ramp charge-to-breakdown at a cumulative distribution failure percentage is calculated. An exponential current ramp constant and a constant current stress constant at the cumulative distribution failure percentage are calculated. A constant current stress charge-to-breakdown at the cumulative distribution failure percentage is calculated by using a specified current density and the constant current stress constant at the cumulative distribution failure percentage. The constant current stress charge-to-breakdown at the cumulative distribution failure percentage is compared to a specified constant current stress charge-to-breakdown to determine the reliability of the dielectric thin film.

Reliability testing method of dielectric thin film

A method of protecting a well at a floating stage. In a first conductive type substrate, a second conductive type well is formed. A first conductive type heavily doped region and a second conductive type heavily doped region are respectively formed in the first conductive type substrate and the second conductive type well. These two heavily doped regions are electrically connected with each at an early stage of fabrication process to provide a protection from being damaged during subsequent plasma process or other processes. While forming a top metal layer of a multi-level interconnect, these two heavily doped regions are disconnected, that is, open to each other, to obtain a better electrical characteristic of the device or the integrated circuit formed on the substrate.

Method of protecting a well at a floating stage

A low triggering voltage PD-SOI (Partially-Depleted Silicon-on-Insulator) electrostatic discharge (ESD) protection structure is disclosed. In one embodiment, the protection structure includes: A semiconductor substrate; a thin film layer separated from a bulk silicon substrate by an insulator inside the semiconductor substrate; a first isolation region formed in the thin film layer; a second isolation region formed in the thin film layer; a first region having a first conductivity type formed in between the first and second isolation region; a second region formed in between the first region and the second isolation region, the second region being of a second conductivity type; a third region formed in between the first isolation region and the first region, the third region being of the first conductivity type; a fourth region formed in between the second isolation region and the second region, the fourth region being of the first conductivity type; a fifth region having an exposed upper surface formed in the first region, the fifth region being of the second conductivity type; a sixth region having an exposed surface formed in the second region, the sixth region being of the second conductivity type; and a seventh region having an exposed upper surface formed in the second region and overlapping the first region, moreover, the seventh region being between the fifth and sixth region and the seventh region being of the first conductivity type. Another embodiment of the present invention is very similar to the previous one, which is also extracted in the present specification.

Low triggering voltage SOI silicon-control-rectifier (SCR) structure

A method for reducing plasma charging damages is disclosed. The method includes the following steps: define cell regions and scribe line regions on a substrate. Then, form a trench region on one of the scribe line regions wherein the bottom part of the trench region is in contact with the substrate. Thereupon fill the trench region with polysilicon substances. After the filling, deposit a pad polysilicon layer on the trench region. Following the pad layer formation, construct an integrated circuit as routine practice. During the circuit fabrication, several channel regions are formed in connection with the pad layer. Next, fabricate various conductive structures on the scribe line regions and link them also to the channel regions. Any excess charge in the scribe line region would be collected by the conductive structures and directed by the channel region to the trench region for grounding. Upon completion of the device fabrication, insulate the process to prevent charges from shifting back to the scribe line regions and damaging the device.

Growing community of inventors

Hsinchu Hsien, Taiwan

Mu-Chun Wang