Taiwan Semiconductor Manufacturing Comp. Ltd.

Mu-Chi Chiang

Kuo-Hua Pan

Ta-Chun Lin

Yi-Shien Mor

Chun-Jun Lin

Kuan-Lin Yeh

Hsiao-Chu Chen

Wen-Chuan Chiang

Min-Hwa Chi

Chia-Chu Liu

Hua Feng Chen

Shu-Hui Wang

Chih-Hao Wang

Jhon Jhy Liaw

Jiaw-Ren Shih

Kuei Shun Chen

Hsien-Chin Lin

Cheng-Ku Chen

Su-Yu Lu

Jhon-Jhy Liaw

Carlos H Diaz

Huan-Just Lin

Kuei-Shun Chen

Min-Chang Liang

Jeng-Ya David Yeh

Hui-Chi Huang

Kuo-Chiang Tsai

Hsiao-Tzu Lu

Bi-Fen Wu

Carlos Hernando Diaz

Minchang Liang

Chao-Jie Tsai

Yu-Sen Chu

Yao-Kwang Wu

Tien-Hung Cheng

Chang-Ku Chen

A semiconductor device includes a source via having a body portion and a barrier layer surrounding the body portion, and the body portion is in physical contact with the source contact. Furthermore, the barrier layer includes at least one sidewall section separating the source via from an adjacent via structure. As such, the via to via leakage may be prevented. Overall, by providing a semiconductor device having the above structures, the contact resistance is reduced, and the device performance is further improved.

Semiconductor device and method of fabricating the same

A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

Isolation structure for preventing unintentional merging of epitaxially grown source/drain

A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

Isolation structure for isolating epitaxially grown source/drain regions and method of fabrication thereof

Isolation structure for for isolating epitaxially grown source/drain regions and method of fabrication thereof

A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.

Substrate resistor and method of making same

A transistor including a gate structure with a first portion and a second portion; the first and second portions each have a first edge and an opposing second edge that are substantially collinear. The gate structure also includes an offset portion interposing the first portion and the second portion. The offset portion has a third edge and an opposing fourth edge. The third edge and the fourth edge are non-collinear with the first and second edges of the first and second portions of the gate structure. For example, the offset portion is offset or shifted from the first and second portions.

Semiconductor device with biased feature

A semiconductor structure includes a resistor on a substrate formed substantially simultaneously with other device elements, such as one or more transistors. A diffusion barrier layer deposited on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor in a substantially similar manner as that used to form the gate of the transistor. The filler material is removed.

A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.

FinFETs and methods for forming the same

A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 &#x212b;, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.

Control fin heights in FinFET structures

A method of fabricating a semiconductor device includes forming a plurality of line element on a provided substrate. The plurality of line elements includes a first line element having a first region having a first width and a biased region having a second width. The second width different than the first width. Spacer elements are then formed abutting sidewalls of each of the plurality of line elements including the biased region where the spacer elements may be shifted. After forming the spacer elements, the plurality of line elements from the substrate are removed from the substrate. An underlying layer is etched using the spacer elements after removing the plurality of line elements.

A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

Field effect transistors and method of forming the same

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Hsin-Chu, Taiwan

Mu-Chi Chiang