Motorola Corporation

Texas Instruments Corporation

Mousumi Bhat

Michael P Woo

Michael C Smayling

Giovanni Santin

Mark Douglas Hall

David L O'Meara

Stanley Michael Filipiak

Terry Grant Sparks

Yeong-Jyh Tom Lii

Craig S Lage

Georges Falessi

Arkalgud R Sitaram

Andrew G Nagy

T P Ong

Larry E Frisa

Iano D'Arrigo

Carol M Gelatos

Giulio Giuseppe Marotta

Donald J Redwine

A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects ( and ), wherein each local interconnect ( ) cross couples the inverters of the SRAM and is formed within a single opening ( ). Also, interconnect portions ( ) of word lines are laterally offset from silicon portions ( ) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Semiconductor device, memory cell, and processes for forming them

Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (,) away from a conductor (,) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (,) is recessed from the edge of the opening (,). When forming a nitride layer (,) within the opening (,), conductive nodules (,) are formed from a portion of the refractory metal containing material (,) such that the conductive nodules (,) lie within the recession (,). In another embodiment, an oxide layer (,) is formed adjacent to the refractory metal containing material (,) before forming a nitride layer (,).

Contact structure and process for formation

A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (,and,), wherein each local interconnect (,) cross couples the inverters of the SRAM and is formed within a single opening (,). Also, interconnect portions (,) of word lines are laterally offset from silicon portions (,) of the same word line, so that the interconnect portions do not interfere with bit line connections.

Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region

Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive modules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

Method of making a contact structure

A low voltage flash EEPROM X-Cell includes an array of memory cell transistors (24) that constitute asymmetric floating gate memory cells wherein programming is achieved on only one side of the memory cells (24). The programming side of each of the memory cells (24) is connected to one of a plurality of Column Lines (28) at nodes (30). Each node (30) shares the programming side of two of the memory cells (24) and the non-programming side of two of the memory cells (24). The control gates of each of the memory cells (24) are connected to Word Lines (26) associated with rows of the array. To Flash Write all of the memory cells (24), the Column Lines (38) are connected to a negative medium voltage and the row lines (26) are connected to a positive medium voltage. To selectively erase one of the memory cells (24), the Column Line (28) associated with the programming side of the select memory cell transistor is connected to a positive medium voltage and the associated line (26) is connected to a positive Read voltage. The remaining Word Lines are connected to a negative Read voltage and the remaining Column Lines (28) are connected to a zero volt level.

Low voltage flash EEPROM C-cell using fowler-nordheim tunneling

A non-volatile memory cell 10 is disclosed herein. The cell is formed in a first semiconductor region 12 of a first conductivity type. A second semiconductor region 14 of a second conductivity type formed over the first semiconductor region 12. A third semiconductor region 16 of the first conductivity type formed over the second semiconductor region 14. In the preferred embodiment, the second and third regions 14 and 16 are well regions formed within the first region 12. Other regions such as epitaxially grown layers can also be used. First and second source/drain regions 18 and 20 are formed within the third semiconductor region 16. These second source/drain regions 18 and 20 are separated by a channel region 22. A floating gate 26 overlies at least a portion of the channel region 22 while a control gate 30 overlies the floating gate 26.

Non-volatile memory cell and level shifter

A transistor device 10 formed in a semiconductor layer 12 is disclosed herein. A first source/drain region 14 is formed in the semiconductor layer 12. A second source/drain region 16 is also formed in the semiconductor layer 12 and is spaced from the first source/drain region 14 by a channel region 18. The second source/drain region 16 includes (1) a lightly doped portion 16b adjacent the channel region 18 and abutting the top surface, (2) a main portion 16a abutting the top surface and spaced from the channel region 18 by the lightly doped portion 16b, and (3) a deep portion 16c formed within the layer 12 and spaced from the top surface by the lightly doped portion 16b and the main portion 16a. A gate electrode 20 is formed over at least a portion of the channel region 18 and insulated therefrom.

Field effect transistor with a lightly doped drain

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Austin, TX, United States of America

Mousumi Bhat