Spin Memory, Inc.

Spin Transfer Technologies, Inc.

Mourad El-Baraji

Neal Berger

Benjamin S Louie

Lester Crudele

Daniel L Hillman

Ben Louie

Barry Hoberman

A method for correcting bit defects in an STT-MRAM memory is disclosed. The method includes reading a codeword in the STT-MRAM memory, wherein the STT-MRAM memory includes a plurality of codewords, wherein each codeword includes a plurality of redundant bits. Further, the method includes mapping defective bits in the codeword to redundant bits of the plurality of redundant bits based on a mapping scheme, wherein the mapping scheme is operable to determine a manner in which the defective bits in the codeword are to be mapped to the redundant bits. Finally, the method includes replacing the defective bits in the codeword with corresponding mapped redundant bits.

Over-voltage write operation of tunnel magnet-resistance ('TMR') memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques

A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register

A memory device includes a write port, a read port, source lines, bit lines, and word lines orthogonal to the bit lines. The memory device also includes memory cells that can be arrayed in columns that are parallel to the bit lines and in rows that are orthogonal to the bit lines. The memory cells are configured so that a write by the write port to a first memory cell in a column associated with (e.g., parallel to) a first bit line and a read by the read port of a second memory cell in a column associated with (e.g., parallel to) a second, different bit line can be performed during overlapping time periods (e.g., at a same time or during a same clock cycle).

Multi-port random access memory

A method for correcting bit defects in an STT-MRAM memory is disclosed. The method comprises executing a read before write operation in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. The read before write operation comprises reading a codeword and mapping defective bits in the codeword. Further, the method comprises replacing the defective bits in the codeword with a corresponding redundant bit and executing a write operation with corresponding redundant bits in place of the defective bits.

On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects

A method for correcting bit defects in a memory array is disclosed. The method comprises determining, during a characterization stage, a resistance distribution for the memory array by classifying a state of each bit-cell in the memory array, wherein the memory array comprises a plurality of codewords, wherein each codeword comprises a plurality of redundant bits. Further, the method comprises determining bit-cells in the resistance distribution that are ambiguous, wherein ambiguous bit-cells have ambiguous resistances between being high or low bits. Subsequently, the method comprises forcing the ambiguous bit-cells to short circuits and replacing each short-circuited ambiguous bit-cell with a corresponding redundant bit from an associated codeword.

Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them

A method for correcting bit defects in a memory array is disclosed. The method comprises determining a margin area associated with a resistance distribution for the memory array, wherein the resistance distribution comprises a distribution of bit-cell resistances for all bits comprising the memory array, wherein the margin area is a bandwidth of bit-cell resistances centered around a reference point associated with a sense amplifier, wherein the bit-cell resistances of memory bit-cells associated with the margin area are ambiguous. The method further comprises forcing the bit-cell resistances of memory bit-cells associated with the margin area to short circuits. Finally, the method comprises replacing each short-circuited memory bit-cell with a corresponding redundant bit in the codeword associated with the short-circuited memory bit-cell.

Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers

A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. Further, the memory device comprises an x decoder circuit coupled to the memory array for decoding an x portion of a memory address for the memory array and a y multiplexer circuit coupled to the memory array and operable to simultaneously multiplex across the memory array based on two y portions of memory addresses and, based thereon with the x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of the memory array, wherein the x decoder and the y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to the memory array.

Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank

A memory pipeline for performing a write operation in a memory device is disclosed. The memory pipeline comprises an input register operable to receive a first data word and an associated address to be written into a memory bank. The memory pipeline also comprises a pre-read register of the first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register and further operable to pre-read a second data word stored in the memory bank at the associated address. Finally, the memory pipeline comprises a write register of the second pipe-stage operable to receive the first data word, the associated address and mask bits from the pre-read register, wherein the write register is further operable to use information from the mask bits to write the first data word into the memory bank by changing those bits in the first data word that differ from the second data word.

Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. Further, the method comprises writing a second plurality of data words and associated memory addresses into a cache memory, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The method also comprises detecting a power down signal and responsive to the power down signal, and before the memory device is powered down, processing data words of the second plurality of data words and associated memory addresses through the pipeline to write data into the memory bank. Finally, the method comprises powering down the memory device.

Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. Further, the method comprises writing a second plurality of data words and associated memory addresses into a cache memory, wherein the cache memory is associated with the memory bank and wherein further each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The method also comprises detecting a power down signal and responsive to the power down signal, transferring the second plurality of data words and associated memory addresses from the cache memory into a secure memory storage area reserved in the memory bank. Finally, the method comprises powering down the memory device.

Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register

Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.

Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words and associated memory addresses into a cache memory, and wherein each data word of the second plurality of data words is associated with a pending operation. Additionally, the method comprises detecting a power up signal and responsive to the power up signal, transferring the second plurality of data words and associated memory addresses from the secure memory storage area to the cache memory. Finally, responsive to the transferring, and before the memory device is powered up, the method comprises processing the second plurality of data words and associated memory addresses from the cache memory to the pipeline for writing data to the memory bank during power up.

Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device

An advantageous write verify operation for bipolar memory devices is disclosed. The verify operation is performed under the same bias conditions as the write operation. Thus, the verify operation reduces disturb conditions caused when verify operation is performed in opposite bias to write operation. The advantageous write verify operation may be performed with control logic on source and bit lines. In another embodiment, the advantageous write operation is performed with mux coupled to control logic. The mux determines whether verify (0) or verify (1) operation should be performed based on data in a program latch. Moreover, the mux may select bias conditions for read operations based on a register bit. Trim circuits optionally provide guard banding and modify reference voltages for verify operations performed in opposite polarity to normal read operation.

Method and apparatus for bipolar memory write-verify

A memory pipeline for performing a write operation in a memory device is disclosed. The memory pipeline comprises an input register operable to receive a first data word and an associated address to be written into a memory bank. The pipeline also comprises a first write register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register, wherein the first write register is further operable to perform a first attempt at writing said data word into the memory bank. Further, the pipeline comprises a second write register of the second pipe-stage coupled to the first write register and operable to receive the first data word and the associated address from the first write register, wherein the second write register is further operable to perform a second attempt at writing the first data word into the memory bank at the location corresponding to the associated address.

Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers

A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a plurality of addressable memory cells configured in a plurality of segments wherein each segment contains N rows per segment, wherein the memory bank comprises a total of B entries, and wherein the memory cells are characterized by having a prescribed word error rate, E. Further, the device comprises a pipeline comprising M pipestages and configured to process write operations of a plurality of data words addressed to a given segment of the memory bank. The device also comprises a cache memory comprising Y number of entries, the cache memory associated with the given segment of the memory bank, and wherein the Y number of entries is based on the M, the N and the prescribed word error rate, E, to prevent overflow of the cache memory.

Growing community of inventors

Fremont, CA, United States of America

Mourad El-Baraji