Via Technologies, Inc.

Moriss Kung

Kwun-Yao Ho

Kwun Yao Ho

Kwun-Yo Ho

Wen-Yuan Chang

Chi-Hsing Hsu

Jimmy Hsu

Lin-Chou Tung

Jackie Fu

Terry Ku

Andy Liao

Chia-Jung Chang

Hsueh Chung Shelton Lu

Kun-Yao Ho

A multi-chip package structure is provided with a first chip, a substrate adjacent to the first chip, a plurality of contacts connecting the first chip and the substrate, a second chip disposed between the first chip and the substrate and connecting to the first chip, and a underfill film, wherein the underfill film covers the contact to isolate the contact from the second chip, wherein an empty space is defined by the second chip and the substrate so that the second chip does not contact the substrate.

Multi-chip package

A chip package including a chip, a package substrate, and a plurality of bumps is provided. The chip has a plurality of chip pads disposed on a surface of the chip. The package substrate has a plurality of first substrate pads, a plurality of second substrate pads, and a surface bonding layer. The first substrate pads and second substrate pads are disposed on a surface of the package substrate. The surface bonding layer is disposed on the first substrate pads and second substrate pads, and covers a part of each second substrate pad. The bumps are respectively disposed between the chip pads and the surface bonding layer. The chip is electrically connected to the package substrate through the bumps. Each first substrate pad is electrically connected to one of the bumps, and each second substrate pad is electrically connected to at least two of the bumps.

Chip package

A manufacturing process of a chip package structure is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure with high-density bonding pads and fine pitch circuit is formed over a hard support base plate having a large area and high degree of planarity. A die is attached to a top surface of the multi-layered interconnection structure. A plurality of opening is formed on a bottom surface of the support base plate. Contacts are positioned into the openings in the support base plate such that the contacts are electrically connected to an inner circuit within the multi-layered interconnection structure.

Manufacturing process of a chip package structure

The present invention provides a chip and its manufacturing methods and applications. Regarding the chip, there are several solder bumps on the backside of the chip. The difference of the invented chip from the convention chips is that the solder bumps are embedded in an insulting layer and a thermal-plastic material layer of the invented chip backside and separated by a conductive layer from the insulting layer and thermal-plastic material layer. Additionally, there are some end members in the insulting layer, and the end member corresponds to one solder bump. Through the present invention, chips with different functions can be integrated together, so that the needs for having portable communication devices lighter and smaller would be met.

Chip and manufacturing method and application thereof

A multi-conducting through hole structure is provided. The multi-conducting through hole structure has a substrate, at least two signal lines and at least a reference line. The substrate has a through hole passing therethrough. The signal lines are disposed on a portion of an inner surface of the through hole and extended through the through hole. The reference line is disposed on a portion of the inner surface of the through hole and extended through the through hole, wherein the reference line is disposed between the lines for signal. Because the signal lines are separated by the reference line, the electromagnetic coupling generated by signals can be reduced to lower the cross-talk interference between signals passing through the through hole, so as to promote the signal-transmission quality.

Multi-conducting through hole structure

A chip package includes a chip, a carrier, and at least a bump connecting structure for connecting the chip to the carrier. The bump connecting structure includes a first metal bump disposed on a chip pad of the chip and has a first height relative to a passivation layer of the chip, a second metal bump disposed on a carrier pad of the carrier and has a second height relative to a solder mask layer of the carrier, and a middle metal part disposed between the first and the second metal bumps. The sum of the minimum distance between the first and the second metal bumps, the first height of the first metal bump, and the second height of the second metal bump is less than 60 micrometers. The melting point of the middle metal part is lower than that of the first and the second metal bumps.

Chip package and bump connecting structure thereof

A build-up layer packaging comprising a first ceramic substrate, a second ceramic substrate, and a circuit layer is provided. The first ceramic substrate has a through hole to dispose a die therein. The second ceramic substrate, attached to a common lower surface of the ceramic substrate and the die, further has a plurality of openings to expose the pads of the die. The openings are filled with plugs electrically connecting to the pads. The circuit layer is formed under the second ceramic substrate to transmit signals generated by the die outward.

Low coefficient of thermal expansion build-up layer packaging and method thereof

A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by deploying a simple, fast film-coating technique. Therefore, there is no need to plate a Ni/Au layer on the bonding pads or contacts using expensive electroplating equipment for preventing oxidation and there is no need to fabricate plating lines on the chip carrier or reserve space for laying out the plating lines. Thus, the cost for fabricating the chip carrier is reduced, the effective area of the chip carrier is increased and the electrical performance of the chip carrier is improved.

Chip carrier with oxidation protection layer

A process for mounting conductive blocks on a surface of a substrate is disclosed wherein the substrate may be an IC chip, carrier, or a PCB. An adhesive layer is formed on each of the pads of the substrate. Thereafter, a plurality of conductive blocks are scattered on the surface of the substrate. The conductive blocks are vibrated such that only one of the conductive blocks is attached to the adhesive layer of each pad. After removing the un-attached conductive blocks from the surface of the substrate, and the remaining conductive blocks become the conductive blocks for electrical connection.

Conductive block mounting process for electrical connection

A stacked multi-chip package comprising a substrate, a first chip, a lead frame, and a second chip is provided. The first chip is placed on and electrically connected with the substrate. The lead frame is placed on the substrate and forming a space therebeneath to accommodate the first chip. The second chip is placed to the lead frame and electrically connected with the substrate through the lead frame.

Stacked multi-chip package

An integrated circuit package includes a balanced-part structure. The condition of thermal stress of chips connected on a substrate decides the amount, locations, weights, and the material of at least a balanced-part fastened on a substrate. The balanced-part is fastened on the substrate to balance stress distribution before an adhering heat sinks process and a packaging molding compound process. The balanced-part also decreases thermal stress affection and avoid warpage defects of the integrated circuit packages.

Integrated circuit package with a balanced-part structure

A high performance thermally enhanced package and method of fabricating the same is provided. A chip (a wire bond chip or a flip chip) and a carrier (lead frame or tape carrier) are bonded together using flip-chip technology and thermal compression. The chip and the carrier are encapsulated using a molding compound. The package has a smaller overall size and the capacity to withstand electromagnetic interference.

High performance thermally enhanced package and method of fabricating the same

This invention relates to an integrated circuit package and a method for the same, especially relates to the integrated circuit package without a solder mask and the method for the same. A solder wettable metal is used as the material of the first solder pad and a non-wettable insulating layer is formed on the top surface and sidewalls of the metal layer, which is not solder pads, in the integrated circuit packages without a solder mask of the present invention to avoid short circuit defects and to increase a circuit density and reliability of the integrated circuit packages.

Integrated circuit packages without solder mask and method for the same

An electrical package and manufacturing method thereof is provided. A high stiffness, high electrical conductivity, low coefficient of thermal expansion and high thermal conductivity support substrate is used as an initial layer for building the package. A multilayer interconnection structure is formed over the support substrate. Thereafter, a plurality of openings is formed over the support substrate. The openings expose a plurality of bonding pads on a bottom surface of the multi-layer interconnection structure. An electronic device is set up over the multi-layer interconnection structure. Contacts are formed inside the opening over the bonding pads.

Electrical package capable of increasing the density of bonding pads and fine circuit lines inside a interconnection

A packaging substrate without plating bar and a method of forming the same is provided. A substrate is firstly provided with circuit patterns formed thereon. Then, solder masks are formed to define connecting points on the circuit patterns. Afterward, the openings of the solder mask on a bottom surface of the substrate are filled with solder material. Thereafter, a seed layer is formed on the bottom surface of the solder mask and the solder material, and then a passivation layer is formed on a surface of the seed layer. Finally, a plating process is carried out by using the seed layer to input cathode electric level to form metal pads on the defined connecting points on the upper surface of the substrate.

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Hsin-Tien, Taiwan

Moriss Kung