Samsung Electronics Co., Ltd.

Moosung Kim

Ohsuk Kwon

Kitae Park

Dongku Kang

Ji-sang Lee

Kihwan Choi

Dawoon Jung

Sungsoo Lee

Jae-Duk Yu

Jaewoo Im

Hansoo Kim

Tae-young Kim

Sang-Soo Park

Youngho Lim

Doogon Kim

Sungwhan Seo

Gyosoo Choo

Ji-Sang Lee

Taekyun Kang

Minjae Seo

Seung-Gum Kim

Jin-young Chun

A non-volatile memory device includes: a memory cell; a bit line connected to the memory cell; a first cross coupled inverter for storing data sensed from the memory cell through a sensing node connected to the bit line; a first transistor and a second transistor respectively connected to respective ends of the first cross coupled inverter and respectively transmitting a ground voltage to respective ends of the first cross coupled inverter; and a control circuit for operating the first transistor and the second transistor at least once for at least one of an initialize period in which the sensing node is discharged and a precharge period in which the bit line is precharged.

Page buffer circuit and memory device including the same

An operating method is for a memory device which controls a nonvolatile memory. The operating method includes managing a program depth bit map indicating an upper page program state of each of a plurality of word lines of the nonvolatile memory in response to an external write request, and outputting one of a plurality of different read commands to the nonvolatile memory based on information of the program depth bit map corresponding to a word line to be accessed in response to an external read request.

Memory controller and memory system including the same

A nonvolatile memory device includes a substrate, a plurality of memory cells stacked in a direction perpendicular to the substrate, word lines connected to the memory cells, a ground select transistor between the memory cells and the substrate, a ground select transistor between the memory cells and the substrate, a ground select line connected to the ground select transistor, a bit line on the memory cells, and a string select transistor between the memory cells and the bit line. In an erase operation, the ground select line is floated at a time when a specific time passes after the erase voltage is provided to the substrate. And the ground select line is floated at different times depending on a temperature.

Nonvolatile memory device and method of erasing the same

A latch management method of a storage device includes permitting the storage device to enter a reduced power mode in which the storage device operates with a reduced power. The method includes reading initial latch data stored in the at least one nonvolatile memory device in response to the entering operation. The method includes setting latches associated with the at least one nonvolatile memory device based on the read initial latch data.

Storage device and latch management method thereof

Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

Methods of operating nonvolatile memory devices that support efficient error detection

A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected level of the program voltage.

Method of programming non-volatile memory device and non-volatile memory device using the same

A method of reading a nonvolatile memory device comprises applying a read voltage to a memory cell array to read selected memory cells, counting a number of the selected memory cells that have a threshold voltage higher or lower than the read voltage, and comparing the counted number with a reference value to determine a number of bits stored in the selected memory cells.

Nonvolatile memory device performing read operation with variable read voltage

A negative voltage generator includes a direct current voltage generator configured to generate a direct current voltage, a reference voltage generator configured to generate a reference voltage, an oscillator configured to generate an oscillation clock, a charge pump configured to generate a negative voltage in response to a pump clock, and a voltage detector. The voltage detector is configured to detect the negative voltage by comparing a division voltage, obtained by voltage dividing the direct current voltage, with the reference voltage, and to generate the pump clock corresponding to the detected negative voltage based on the oscillation clock.

Negative voltage generator, decoder, nonvolatile memory device and memory system using negative voltage

Nonvolatile memory devices include a two-dimensional array of nonvolatile memory cells having a plurality of memory cells of unequal size therein. These memory cells may include those that have unequal channel widths associated with respective word lines and those having unequal channel lengths associated with respective bit lines that are connected to corresponding strings of nonvolatile memory cells (e.g., NAND-type strings). Control circuitry is also provided that is electrically coupled to the two-dimensional array of nonvolatile memory cells. This control circuitry may operate to concurrently program first and second nonvolatile memory cells having unequal sizes from an erased state (e.g., logic 1) to an equivalent programmed state (e.g., logic 0). This is done by establishing unequal first and second word line-to-channel region voltages in the first and second nonvolatile memory cells, respectively, during an operation to program a row of memory cells in the two-dimensional array of nonvolatile memory cells, which includes the first and second nonvolatile memory cells of unequal size.

Nonvolatile memory devices having memory cell arrays with unequal-sized memory cells and methods of operating same

A word line voltage generating method of a flash memory which includes generating a program voltage using a positive voltage generator; generating a plurality of negative program verification voltages corresponding to a plurality of negative data states using a negative voltage generator; and generating at least one or more program verification voltages corresponding to at least one or more states using the positive voltage generator. Generating a plurality of negative program verification voltages includes generating a first negative verification voltage; discharging an output of the negative voltage generator to become higher than the first negative verification voltage; and performing a negative charge pumping operation until an output of the negative voltage generator reaches a second negative verification voltage level.

Flash memory device and wordline voltage generating method thereof

A nonvolatile memory device (NVM), memory system and apparatus include control logic configured to perform a method of applying negative voltage on a selected wordline of the NVM. During a first time a first high voltage level is applied to the channel of a transistor of a address decoder and a ground voltage is applied to the well of the transistor. And, during a second time a second high voltage level is applied to the channel of the transistor, and within the second time interval a first negative voltage is applied to the well of the transistor. The first high voltage level is higher than the second high voltage level, and a voltage applied on the selected wordline is negative within the second time interval.

Growing community of inventors

Yongin-si, South Korea

Moosung Kim