Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Moon-seung Yang

Seong-ho Cho

Mohammad Rakib Uddin

Sung-Hun Lee

Myoung-jae Lee

Sang-moon Lee

Jun-youn Kim

Dong-Soo Lee

David Seo

Taek Woon Kim

Ji-hyun Hur

Eui-chul Hwang

Young-soo Park

Jae-Chul Park

Su-hee Chae

Kyoung-kook Kim

Joo-sung Kim

Hyung-su Jeong

Yoon-Dong Park

Young-Gu Jin

In-sung Joe

Dae-kil Cha

Jung-hoon Shin

Jee-soo Chang

The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

Semiconductor device and method of fabricating the same

A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.

Substrate structure, complementary metal oxide semiconductor device, and method of manufacturing complementary metal oxide semiconductor device

A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer.

Semiconductor buffer structure, semiconductor device including the same, and manufacturing method thereof

Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. In the CMOS device, a buffer layer is disposed on a silicon substrate, and a first layer including a group III-V material is disposed on the buffer layer. A second layer including a group IV material is disposed on the buffer layer or the silicon substrate while being spaced apart from the first layer.

Complementary metal oxide semiconductor device and method of manufacturing the same

An athermal optical modulator includes a waveguide, a ring resonator configured to receive light input from the waveguide and output modulated light to the waveguide, the ring resonator including a ridge unit located at a center of the ring resonator in a vertical section, a first contact connected to one side of the ridge unit and a second contact connected to the other side of the ridge unit, the first contact and the second contact forming paths for applying electricity to the ring resonator to form an electric field in the ring resonator, and a polymer layer covering the ridge unit.

Athermal optical modulator and method of manufacturing the same

A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

A nanostructured light-emitting device including: a first type semiconductor layer; a plurality of nanostructures each including a first type semiconductor nano-core grown in a three-dimensional (3D) shape on the first type semiconductor layer, an active layer formed to surround a surface of the first type semiconductor nano-core, and a second type semiconductor layer formed to surround a surface of the active layer and including indium (In); and at least one flat structure layer including a flat-active layer and a flat-second type semiconductor layer that are sequentially formed on the first type semiconductor layer parallel to the first type semiconductor layer.

Nanostructured light-emitting device

Provided is a light emitting diode (LED) manufactured by using a wafer bonding method and a method of manufacturing a LED by using a wafer bonding method. The wafer bonding method may include interposing a stress relaxation layer formed of a metal between a semiconductor layer and a bonding substrate. When the stress relaxation layer is used, stress between the bonding substrate and a growth substrate may be offset due to the flexibility of metal, and accordingly, bending or warpage of the bonding substrate may be reduced or prevented.

Light emitting device and method of manufacturing the same

An optical amplifying medium, a method of manufacturing the optical amplifying medium are provided, and an optical device comprising the optical amplifying medium. The optical amplifying medium includes a multi-layer structure in which a first material layer doped with an activator and a second material layer that comprises a sensitizer are stacked.

Optical amplifying medium, method of manufacturing the optical amplifying medium, and optical device comprising the optical amplifying medium

Provided is a method of manufacturing a light emitting device from a large-area bonding wafer by using a wafer bonding method using. The method may include forming a plurality of semiconductor layers, each having an active region for emitting light, on a plurality of growth substrates. The method may also include arranging the plurality of growth substrates on which the semiconductor layers are formed on one bonding substrate and simultaneously processing each of the semiconductor layers formed on each of the growth substrates through subsequent processes. The bonding wafer may be formed of a material that reduces or prevents bending or warping due to a difference of thermal expansion coefficients between a wafer material, such as sapphire, and a bonding wafer. According to the above method, because a plurality of wafers may be processed by one process, mass production of LEDs may be possible which may reduce manufacturing costs.

Growing community of inventors

Hwaseong-si, South Korea

Moon-seung Yang